Earticle

The term “Ubiquitous Medical Sensor Networks” (UMSN) is used to describe networks of intelligent sensor nodes that could be deployed “anywhere, anytime, by anyone and anything ” . Earlier research shows that it is highly suitable for monitoring purposes in military use and also biomedical applications. However, there isn’t any flexible and robust communication infrastructure to integrate these devices into an emergency care setting. An efficient wireless communication substrate for medical devices that addresses ad hoc or fixed network formation, naming and discovery, security and authentication, as well as filtration and aggregation of vital sign data need to be studied. This research is aimed at developing a system that is able to provide continuous monitoring of patients outside the hospital environment.

BIST is a design technique that allows a circuit to test itself. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. Due to the randomness properties of Linear Feedback Shift Registers (LFSRs), this requires very little hardware overhead. In this paper, structure design and optimization of a Built-In Self-Test (BIST) design based on twodimensional (2-D) Linear Feedback Shift Registers (LFSRs) are described. The 2-D LFSRs can generate both precomputed test patterns (for detecting random-pattern-resistant faults) and random patterns (for detecting random-pattern-detectable faults) and have the advantages of high fault coverage and at-speed testing. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit. For LFSR-Reseeding Scheme takes advantage of the fact that the number of transitions in a test cube is always less than the number of blocks that do not contain transitions, the logic value fed into the scan chain is simply held constant. This approach reduces the number of transitions in the scan chains and thus minimizing power consumption.

The main aim of this paper is to design and implement a high speed, low complexity and polymorphic architecture for reconfigurable folded wavelet filters. 5/3 wavelet results are incorporated into the 9/7 data path which reduces the number of adders compared to other solutions and also allows on the fly switching between the filters. The proposed work is to improve the speed of this reconfigurable architecture. This is accomplished by scheduling. A weight based scheduling algorithm has been used in this paper. This is an analysis method to improve inter task communication as well as data dependencies among tasks which will reduce the overall communication overhead and processing time.

Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). In this paper a novel photonic crystal power/ground layer (PCPL) is proposed to efficiently suppress the power/ground bounce noise (P/GBN) or simultaneously switching noise (SSN) in high-speed digital circuits. The PCPL is designed by periodically embedding high dielectric-constant rods into the substrate between the power and ground planes. The PCPL can efficiently suppress the high frequency noise and its radiated EMI generated be the SSN (over 60 dB) with broad stop band bandwidth (totally over 4 GHz below the 10-GHz range, and in the time domain, the P/GBN can be significantly reduced over 90%. The PCPL not only performs good power integrity, but also keeps good signal quality with significant improvement on eye patterns for high-speed signals with via transitions. In addition, the proposed designs perform low radiation of electromagnetic interference caused by the SSN within the stop bands. These extinctive behaviors both in signal integrity and electromagnetic compatibility are demonstrated numerically and experimentally.

Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications.So due to this not much development had taken place in this field. But nowadays floating point divider has become indispensable and increasingly important in many modern applications. Most of the previous implementation required much larger area and latencies. In this paper an area optimized design and implementation of a sequential and pipelined double precision floating point divider is presented. This design is then mapped onto an FPGA chip without utilizing any of its embedded features

For more than 30 years, the IC industry has followed a steady path of constantly shrinking the device geometries and increasing chip size. A new gate structure called the dual material gate (DMG) MOSFET was proposed which eliminates the effects of reduction of chip size. A 2D analytical approach of DMG is proposed in this paper and the solution to the Poisson equation is obtained using parabolic expansion method. Using the boundary conditions, the surface potential and electric field potential distribution is obtained for different work function and channel lengths.

Density, viscosity and ultrasonic velocity have been measured for binary liquid mixtures containing Methylmethacrylate+2-Methoxy ethanol, Methylmethacrylate +2-Ethoxy ethanol, Methyl methacrylate+2 Butoxy ethanol at 303K. The adiabatic compressibility, free length, free volume, internal pressure, relaxation time, acoustic impedance and Gibbs’s free energy values have been calculated from the experimental data. These parameters are used to discuss the molecular interactions in the mixtures.