Earticle

The security of the cyberspace is both a national and an international issue concerned with different levels including: people, enterprises, and governments. It is also associated with different activities including: technical, economic, social and political. As a result, interest in the development of sound national information security policies is becoming of increasing importance. This paper aims at providing a comprehensive approach for this development. For this purpose, the paper is divided into two main parts: the first reviews key related issues in order to establish the necessary background for the work; while the second describes the target approach. The approach has four main dimensions: a structured scope that integrates all the issues concerned; a development process that deals with responding to security requirements on continuous basis; security measures and standards for assessments and benchmarking; in addition to past experience and knowledge sharing for improvements. It is hoped that the approach will become a base for the development and continuous improvement of a national information security policies, not only for Saudi Arabia, but also for other countries in different parts of the world.

Data mining is involved in procedures by which patterns are extracted from data. This process has become increasingly important to map data patterns to useful information that can be used to predict future traffic analyses. Other areas were data mining can be used include: fraud detection, marketing, congestion control, and network expansion consideration. Data mining involves capturing and gathering random data from the flow of information passing through a certain trunk or node and from a statistical point of view, it can only be meaningful if enough samples are gathered. The results achieved from a proper deployment of a data mining method provide valuable insights to how busy a node is, the average oneway and end-to-end delays, and the average size of the packets.. This paper contains the results from capturing live wired traffic and analyzing the statistical values.

This paper presents a novel method for the objective quality evaluation of letterings at the example of laser markings. The proposed method enables an automated quality evaluation during random inspection of small quantities of frequently changing items. The markings are segmented from the image within a first step and compared against a master piece in the second step. Each character and contour is evaluated with regard to completeness, contrast, edge width and homogeneity according to quality criteria based on the human visual perception. Thus our approach provides an user-independent evaluation method with high repeatability and reproducibility for its industrial application.

In this paper, the use of finite Gaussian mixture modal (GMM) based Expectation Maximization (EM) estimated algorithm for score level data fusion is proposed. Automated biometric systems for human identification measure a “signature” of the human body, compare the resulting characteristic to a database, and render an application dependent decision. These biometric systems for personal authentication and identification are based upon physiological or behavioral features which are typically distinctive, Multi-biometric systems, which consolidate information from multiple biometric sources, are gaining popularity because they are able to overcome limitations such as non-universality, noisy sensor data, large intra-user variations and susceptibility to spoof attacks that are commonly encountered in mono modal biometric systems. Simulation show that finite mixture modal (GMM) is quite effective in modelling the genuine and impostor score densities, fusion based the resulting density estimates achieves a significant performance on eNTERFACE 2005 multi-biometric database based on face and speech modalities.

Unique characteristics of biological systems are described, and similarities are made to certain computing architectures. The security challenges posed by these characteristics are discussed. A method of securely isolating portions of a design using introspective capabilities of a fine-grain self-configurable device is presented. Experimental results are discussed, and plans for future work are given.

As fabrication technology continues to improve, smaller feature sizes allow increasingly more integration of system components onto a single die. Communication between these components can become the limiting factor for performance unless careful attention is given to designing high performance interconnects. Amongst various components of the interconnect, a high-performance arbiter in a scheduler decides the speed of scheduling. An intelligent centralized scheduler is needed to configure the crossbar fairly and with high utilization. The main contribution of this paper is the design and optimization of fast round- robin arbiters and the design of a On-Chip Scheduler embodying I-SLIP algorithm. An iterative, round-robin algorithm, iSLIP can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware. Iterative and noniterative versions of the algorithms are presented, along with modified versions for prioritized traffic. Scheduler is expressed here in verilog RTL and simulation results are presented to indicate the performance of iSLIP under benign and bursty traffic conditions. Prototype and commercial implementations of iSLIP exist in systems with aggregate bandwidths ranging from 50 to 500 Gb/s. When the traffic is nonuniform, iSLIP quickly adapts to a fair scheduling policy that is guaranteed never to starve an input queue. We describe the implementation complexity of iSLIP algorithm in a round robin scheduler which configures 8x8 crossbar. Further, we have synthesized the accept and grant arbiters and optimized its area and timing using TSMC’s library [tcb015ghdbc] with TSMC8k_Conservative wire load model. The request is processed pretty fast and reaches at grant output of the arbiter in 0.59 ns. The total cell area of the proposed arbiter design is 445.Further the scheduler is synthesized to obtain its cell area 20393 while the longest path takes 0.52 ns time. It becomes the most optimized scheduler in an On-Chip Interconnect. The designs were optimized under the same operating conditions with similar area and timing constraints using TSMC’s library [tcb015ghdbc].