Earticle

초록

영어

As fabrication technology continues to improve, smaller feature sizes allow increasingly more integration of system components onto a single die. Communication between these components can become the limiting factor for performance unless careful attention is given to designing high performance interconnects. Amongst various components of the interconnect, a high-performance arbiter in a scheduler decides the speed of scheduling. An intelligent centralized scheduler is needed to configure the crossbar fairly and with high utilization.
The main contribution of this paper is the design and optimization of fast round- robin arbiters and the design of a On-Chip Scheduler embodying I-SLIP algorithm. An iterative, round-robin algorithm, iSLIP can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware. Iterative and noniterative versions of the algorithms are presented, along with modified versions for prioritized traffic. Scheduler is expressed here in verilog RTL and simulation results are presented to indicate the performance of iSLIP under benign and bursty traffic conditions.
Prototype and commercial implementations of iSLIP exist in systems with aggregate bandwidths ranging from 50 to 500 Gb/s. When the traffic is nonuniform, iSLIP quickly adapts to a fair scheduling policy that is guaranteed never to starve an input queue. We describe the implementation complexity of iSLIP algorithm in a round robin scheduler which configures 8x8 crossbar.
Further, we have synthesized the accept and grant arbiters and optimized its area and timing using TSMC’s library [tcb015ghdbc] with TSMC8k_Conservative wire load model. The request is processed pretty fast and reaches at grant output of the arbiter in 0.59 ns. The total cell area of the proposed arbiter design is 445.Further the scheduler is synthesized to obtain its cell area 20393 while the longest path takes 0.52 ns time. It becomes the most optimized scheduler in an On-Chip Interconnect. The designs were optimized under the same operating conditions with similar area and timing constraints using TSMC’s library [tcb015ghdbc].

목차

Abstract
 1. The Scheduling Algorithm:
 2. Arbiters
 3. Programmable Priority Encoder
 4. Scheduler
 5. Constraints:
 6. Testing
 7. Area and Timing Results
 8. Conclusion
 9. Simulation of PPE using XILINX ISE 9.1:
 10. Simulation result of Arbiter using XILINX ISE 9.1:
 11. References

키워드

저자

• Vilas N. Nitnaware [ Department of Electronics Design Technology, Shri Ramdeobaba K. N. Engg. College, Nagpur, India. ]
• Shyam S. Limaye [ Principal, Jhulelal Institute of Technology, Nagpur, India. ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605