The main aim of this paper is to design and implement a high speed, low complexity and polymorphic architecture for reconfigurable folded wavelet filters. 5/3 wavelet results are incorporated into the 9/7 data path which reduces the number of adders compared to other solutions and also allows on the fly switching between the filters. The proposed work is to improve the speed of this reconfigurable architecture. This is accomplished by scheduling. A weight based scheduling algorithm has been used in this paper. This is an analysis method to improve inter task communication as well as data dependencies among tasks which will reduce the overall communication overhead and processing time.
목차
Abstract 1. Introduction 2. The polymorphic architecture 2.1. Lagrange Half Band Filter 2.2. Canonical Signed Digit 2.3. Reconfigurable hardware 3. Proposed work 3.1. Scheduling 4. Simulation result 5. Experimental results 6. Conclusions 7.References
키워드
Polymorphic architectureCanonical signed digitLagrange half band filterreconfigurable hardwarefolding
저자
R.Lavanya [ vlsi signal processing research group(ECE Dept), Amrita school of engineering ]
Saranya B [ vlsi signal processing research group(ECE Dept), Amrita school of engineering ]
보안공학연구지원센터(IJAST) [Science & Engineering Research Support Center, Republic of Korea(IJAST)]
설립연도
2006
분야
공학>컴퓨터학
소개
1. 보안공학에 대한 각종 조사 및 연구
2. 보안공학에 대한 응용기술 연구 및 발표
3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최
4. 보안공학 기술의 상호 협조 및 정보교환
5. 보안공학에 관한 표준화 사업 및 규격의 제정
6. 보안공학에 관한 산학연 협동의 증진
7. 국제적 학술 교류 및 기술 협력
8. 보안공학에 관한 논문지 발간
9. 기타 본 회 목적 달성에 필요한 사업
간행물
간행물명
International Journal of Advanced Science and Technology
간기
월간
pISSN
2005-4238
수록기간
2008~2016
십진분류
KDC 505DDC 605
이 권호 내 다른 논문 / International Journal of Advanced Science and Technology vol.18