Earticle

초록

영어

Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications.So due to this not much development had taken place in this field. But nowadays floating point divider has become indispensable and increasingly important in many modern applications. Most of the previous implementation required much larger area and latencies. In this paper an area optimized design and implementation of a sequential and pipelined double precision floating point divider is presented. This design is then mapped onto an FPGA chip without utilizing any of its embedded features

목차

Abstract
 1. Introduction
 2. Previous work
 3. Double precision floating point divider based on IEEE 754 binary floating point standard
 4. Double precision floating point divider architecture
 5. Pipelining of Double precision floating point divider
 6. Implementation results
 7. Future enhancement
 8. Conclusion
 9. References

키워드

저자

• Shamna.K [ Student , M-Tech VLSI Design Dept. of Electronics and Communication Engineering Engineering ]
• S.R Ramesh [ Assistant. Professor Dept. of Electronics and Communication Engineering Amrita Vishwa Vidyapeetham, Coimbatore, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605