Earticle

초록

영어

Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). In this paper a novel photonic crystal power/ground layer (PCPL) is proposed to efficiently suppress the power/ground bounce noise (P/GBN) or simultaneously switching noise (SSN) in high-speed digital circuits. The PCPL is designed by periodically embedding high dielectric-constant rods into the substrate between the power and ground planes. The PCPL can efficiently suppress the high frequency noise and its radiated EMI generated be the SSN (over 60 dB) with broad stop band bandwidth (totally over 4 GHz below the 10-GHz range, and in the time domain, the P/GBN can be significantly reduced over 90%. The PCPL not only performs good power integrity, but also keeps good signal quality with significant improvement on eye patterns for high-speed signals with via transitions. In addition, the proposed designs perform low radiation of electromagnetic interference caused by the SSN within the stop bands. These extinctive behaviors both in signal integrity and electromagnetic compatibility are demonstrated numerically and experimentally.

목차

Abstract
 1. Introduction
  1.1 Simultaneous Switching Noise.
 2. PCPL MODEL AND DESIGN BY 2-D FDTD METHOD
  2.1 PCPL Concept
  2.2. PCPL Design and Fabrication
 3. PI/SI PERFORMANCE
  3.1. PI Performance
  3.2. SI Performance
 4. DESIGN DIAGRAM
 5. EMI PERFORMANCE
 6. CONCLUSION
 REFERENCES

키워드

저자

• S.M.Ramesh [ Sr. Lecturer, Bannari Amman Institute Of Technology, Sathyamangalam ,India ]
• R.Benschwartz [ PG Scholar, Bannari Amman Institute Of Technology, Sathyamangalam , India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605