BIST is a design technique that allows a circuit to test itself. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. Due to the randomness properties of Linear Feedback Shift Registers (LFSRs), this requires very little hardware overhead. In this paper, structure design and optimization of a Built-In Self-Test (BIST) design based on twodimensional (2-D) Linear Feedback Shift Registers (LFSRs) are described. The 2-D LFSRs can generate both precomputed test patterns (for detecting random-pattern-resistant faults) and random patterns (for detecting random-pattern-detectable faults) and have the advantages of high fault coverage and at-speed testing. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit. For LFSR-Reseeding Scheme takes advantage of the fact that the number of transitions in a test cube is always less than the number of blocks that do not contain transitions, the logic value fed into the scan chain is simply held constant. This approach reduces the number of transitions in the scan chains and thus minimizing power consumption.
보안공학연구지원센터(IJAST) [Science & Engineering Research Support Center, Republic of Korea(IJAST)]
설립연도
2006
분야
공학>컴퓨터학
소개
1. 보안공학에 대한 각종 조사 및 연구
2. 보안공학에 대한 응용기술 연구 및 발표
3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최
4. 보안공학 기술의 상호 협조 및 정보교환
5. 보안공학에 관한 표준화 사업 및 규격의 제정
6. 보안공학에 관한 산학연 협동의 증진
7. 국제적 학술 교류 및 기술 협력
8. 보안공학에 관한 논문지 발간
9. 기타 본 회 목적 달성에 필요한 사업
간행물
간행물명
International Journal of Advanced Science and Technology
간기
월간
pISSN
2005-4238
수록기간
2008~2016
십진분류
KDC 505DDC 605
이 권호 내 다른 논문 / International Journal of Advanced Science and Technology vol.18