Earticle

A selection method of possible code words in channel coding systems is presented. The proposed method is for channel coding of digital communication systems. Measuring the error correction capability with reunion junction, the proposed method has superior performance and low implementation complexity.

Firstly, a novel structure of indoor quad-rotor airship is proposed to overcome the traditional indoor airship shortcomings such as poor balance and lack of buoyancy in this paper. The kinetic model is established according to the design structure and flight characteristics by the principle of Newtonian mechanics and the laws of physics. The force analysis on the quad-rotor airship, including gravity, buoyancy, aerodynamic, wind resistance, propeller force, etc. Secondly, binding Kinetics model, the outer loop position controller and the inner loop attitude controller are designed based on the PID control algorithm. The outer loop position controller includes instantaneous position and velocity, while the inner loop attitude controller includes body angular velocity, Euler angular velocity and Euler angles. The simulation platform is designed by using Matlab/Simulink. The simulation results demonstrate the correctness of the dynamic model and the effectiveness of the control method. Finally, according to the PID’s effect on time-varying system and nonlinear system is not very well perfect, we adopted Lyapunov stability theorem and backstepping algorithm to design the controller and divides the whole system into two return circuits and each circuit are divided into three second-order systems which reduce order number of controller effectively. And the control algorithm achieved good results.

The concatenated codes or the convolutional codes which are often adopted in the communication systems are originally designed to overcome the random independent noise. As such, the performance is severely degraded over the bursty impulsive noise channels. In this paper we compare the bit error rate (BER) performance of the various different channel coding schemes with interleaver over the bursty impulsive noise channels. In particular, we focus on the existence of the bit level and/or the byte level interleavers and show from the extensive simulations that the performance can be different depending on the existence of the interleaver. From our simulations we can see that the concatenated codes with the byte interleaver between the inner and outer codes and the bit interleaver after the inner code gives the best performance among them. For the schemes which include the bit level interleaver, we also observe the interleaving gain versus the interleaver span so that it can be a good guideline to design the communication systems with the concatenated codes.

This paper describes how to design a Galois field GF(28)dividing circuit using double subfield transformation[5]. The circuit is much faster and more efficient than the classical GF(28) divider . Multiplier circuit is used mainly for ECC encoding and for the Encripting machine while the Divider is used for ECC decoding and the Decripting machine. The divider in the paper is designed based on the GF(22) inversing circuit and we applied double subfield transformation. We compared the new design with the classical design in both respects, speed and cost so find the new design is much better than the classical design.

The packet based OFDM (Orthogonal Frequency Division Multiplexing) systems require the fast timing synchronization using a preamble located at the beginning of the received data frame. To detect the symbol timing of the received signal, periodicity of the preamble can be utilized. However, the time varying gain of preamble sample values can affect the performance of the synchronization in case the samples of the beginning part of the packet are involved. This is due to the AGC (Automatic Gain Control) operation at the receiver. Conventional symbol timing detectors use the very last part of the short preamble whose gain level is settled upon the completion of the AGC operation. In this paper the symbol timing detector is proposed using all parts of the short preamble to improve the detection performance keeping the independence of the AGC gain. Simulation results show that the proposed method shows compatible performance for various channel environments.

This paper concerned with a model reduction of infinite dimensional systems by using the singular perturbation approximation. The system considered is that of the exponentially stable linear system with bounded and finite-rank input and output operators such that the balanced realization can be performed on the system. Furthermore, the singular perturbation method is applied to reduce the order of the balanced infinite dimensional systems. A reduced-order model can be obtained by setting to zero of derivative all states corresponding to smaller Hankel singular values. To show the effectiveness of the proposed method, numerical simulations are applied to the heat conduction.

We consider a combined power and rate adaptation scheme in direct-sequence code division multiple access (DS/CDMA) communi- cations over Nakagami fading channels, where the transmission power and the data rate are jointly adapted relative to channel variations. The transmission power proportional to Gp i is allocated to the data trans- mission of user i, where Gi is the channel power gain for user i, and p is a real number, and the data rate is simultaneously adapted so that a desired transmission quality is maintained. We analyze the effect of imperfect channel estimation on the average data rate of the joint adap- tation scheme.

Manycore processor architectures are currently very widely used in almost all computer systems. Furthermore, many computer science department have started to teach parallel programming on manycore system platforms. To best understand the parallel programming on those manycore processors, the classes on manycore processor architecture also have to be provided. However, most current undergraduate computer architecture classes have not yet provided. In this paper, we have design a manycore processor design using a conventional MIPS processor design that is considered as a standard processor architecture model in a traditional undergraduate computer architecture class. Synthesize manycore processor models are developed in 850 lines of Verilog-HDL together with simple parallel applications so students can understand the entire manycore processor design and can learn the basics of the manycore system including underlying communication architecture.

In this paper, we describe the smart metal casting process management system, in which we applied case-based reasoning to find a near optimal process route on the window environment. The metal casting process is complex and variable depends on a kind of metal casting products. Especially, the metal casting industry has a feature which produces small quantities but produces a lot of different types of metal casting products. And we developed the smart metal casting process management system which could show the process route according to the product cases intelligently using the result of case-based reasoning. The experimental result shows that our metal casting process management system schemes achieves more productivity than manual management schemes.