Earticle

This study proposes an energy-efficient framework for non-terrestrial networks (NTNs) integrating a low Earth orbit (LEO) satellite, an unmanned aerial vehicle (UAV)-mounted reconfigurable intelligent surface (RIS), and a terrestrial user. The framework jointly optimizes the UAV’s 3D trajectory, satellite beamforming vectors, and RIS reflection coefficients to maximize energy efficiency (EE), accounting for UAV propulsion energy consumption and Quality of Service (QoS) constraints. The resulting non-convex fractional problem is solved using a low-complexity iterative algorithm combining successive convex approximation (SCA) and second-order cone programming (SOCP). Simulation results reveal up to 35% EE improvement over baseline schemes, highlighting the framework’s scalability and practicality for sustainable NTN systems.

Existing BIM(Building Information Modeling) based energy evaluation tools cannot be utilized enough for the potential performance of BIM because most of them have not provided the integrated model for energy evaluation, assessment of the material, cost of the construction, and so on. This research aims to propose and develop a new application, EcoBIM, to support an integrated evaluation of the energy and cost efficiencies of the design alternatives within the design process. The proposed application functions as a BIM-based evaluation system that calculates energy-savings performance as well as the construction cost of the alternatives at the design stage. This study mainly focuses on the possibilities of developing the proposed technology. We also suggest an advanced design process using the proposed system, corresponding to changes of national regulations in Korea. This study deduce that EcoBIM can allow architects to make suitable decisions regarding energy- and cost-efficient designs. The proposed design process will allow architects not only to check the eco-friendly performance of design alternatives but also predict the operation cost in a certain period in the future. EcoBIM can prevent large-scale design changes required to obtain environmental certification and enable the owner to make an informed decision about the initial investment of construction according to the result of the analysis of the energy requirement at the design stage.

현재의 네트워크 프로토콜은 대부분의 계층에서 Broadcast를 기반으로 설계/구현되어 불필요한 데이터가 overhear 되는 등 에너지 측면에서 비효율적이다. 예를 들어 이더넷 프로토콜의 경우, 전송충돌 감지를 위해 송신자를 제외 한 모든 노드들은 항상 NIC를 Active 상태로 유지해야 하며, overhearing을 통해 자신에게 전송되는 프레임을 인 지해야 한다. 이러한 대기 상태의 유휴 전력 소모를 최소화하기 위해서는 송신자와 수신자만의 Active 상태로 유지 되어야 하며, 패킷 송수신이 발생 시 그 외 노드들은 Idle 상태가 유지되도록 하는 Broadcast 기반이 아닌 Active/Idle 상태 전환을 통한 Unicast 기반의 MAC 프로토콜 설계가 필요하다. 본 논문에서는 이러한 에너지 비 효율성을 관련 연구들의 조사와 실제 네트워크 모니터닝 및 분석들 통해 에너지 효율적인 유선 네트워크 프로토콜 의 필요성을 지적하고 계층 별 네트워크 프로토콜의 설계 방향을 논의한다. 즉, peer-to-peer connection 생성하 는 기존의 네트워크 프로토콜과는 달리 서비스 그룹 별 connection 관리를 통해 동일 context 패킷의 중복 전송을 최소화 하는 에너지 효율적인 네트워크 프로토콜(MAC, 라우팅, 트랜스포트)을 설계가 필요하다.

The current network protocols for wired networks are usually based on message broadcast to detect a peer, which leads to repeatedly overhear the packets not destined to itself. These frequent unnecessary overhearing may cause an huge energy inefficiency in the view of the global Internet. For example, the Ethernet protocol always keeps its NIC alive to sense the bit transmission signal to avoid a collision and should receive even the packets not destined to itself to determine a proper arrival. Thus, to save an energy, a sleep-and-wake mechanism not on broadcast but by on unicast needs to be incorporated. In this paper, we point out the energy inefficiency over the wired network through a related work survey and an analysis in packet monitoring. Based on the observation, we also discuss some energy efficient design policies for MAC, routing, and transport protocols over energy efficient wired networks.

The purpose of this study is to develop a computerized shading simulation program considering solar radiation and to verify its numerical and graphical effectiveness in fenestration system design. Even though the thermal effect of the transmitted solar radiation through fenestration is understood as one of critical factors in building design, it is hardly considered in early design stage because of difficulty in its concept and calculation process. To be widely used by architectural designers in their architectural projects, the program should provide user-friendly graphical interface which can clearly represent the thermal effect of their design as well as proper guideline that can provide accurate simulation results without big burden of user input. The Shaded Fenestration Design(SFD) program has been developed as an energy-effective shading device and window system design program considering effects of shaded solar radiation. For the validation of the program, a physical test box was specially designed and tested to show the accuracy of the program. The comparative tests with widely used computer simulation program(DOE-2) showed that the SFD program with the HDKR model provided more reliable results than DOE-2 program.

In this paper, we propose a fault-tolerant scheduling scheme with energy efficiency for real-time periodic tasks on DVFS-enabled multicore processors. The scheme provides the tolerance of a permanent fault with the primary-backup task model. Also the scheme reduces the energy consumption of real-time tasks with the fully overlapped execution between each primary task and its backup task, whereas most of previous methods tried to minimize the overlapped execution between the two tasks. In order to the leakage energy loss of idle cores, the scheme activates a part of available cores with rarely used cores powered off. Evaluation results show that the proposed scheme saves up to 82% energy consumption of the previous method.

In this paper, we propose an energy-efficient scheduling scheme for real-time periodic tasks on a heterogeneous Grid computing system. The Grid system consists of heterogeneous processors providing the DVFS mechanism with a finite set of discrete clock frequencies. In order to save energy consumption, the proposed scheduling scheme assigns each real-time task to a processor with the least energy increment. Also the scheme activates a part of all available processors with unused processors powered off. Evaluation shows that the proposed scheme saves up to 70% energy consumption of the previous method.

In this paper, laser driver circuit is designed using current mode logic for safe mode interface of laser with devices attached ahead. Furthermore, energy efficient design is realized on FPGA virtex-6 using Low Voltage Differential Signaling technique. The energy efficient design is tested on Hyper Transport Protocol IO standard on FPGA that includes HTP 1.1, HTP 2.0, HTP 2.5, HTP 3.0 and HTP 3.1 having operating frequencies 1 GHz, 10 GHz, 100 GHz, 1 THz and 10 THz respectively. In LVDS, the four voltage swing values are taken2.5V, 1.2V, 0.9V and 0.3V. Laser driver is operated at mentioned hyper transport protocols for each voltage swing value. It is extracted that when laser driver is operated at all HTPs on voltage swing 0.3V; the maximum power reduction is recorded. For HTP 1.1. 87%, for HTP 2.0. 85%, for HTP 2.5. 85%, for HTP 3.0. 86% and for HTP 3.1. 86% power reduction is recorded at LVDS voltage swing 0.3V in comparison with LVDS voltage swing 2.5V. The main contribution of this work is that energy efficient design of laser driver is proposed that consume less power when signal is transferred at different protocols having high frequenciesusing LVDS technique.This laser driver will be integrated with other optical components in system to provide green optical communication. The design is demonstrated using Xilinx 14.3 software package.

Coordinated multi-point (CoMP) has been raised to increase the average cell throughput and the cell-edge user throughput. However, the energy consumption of mobile stations (MSs) is a key problem restricting the wide application of CoMP systems. Considering the energy consumption of feeding back channel state information (CSI) by MSs and the influence of CSI accuracy on the throughput of system, it is proposed to measure the relationship between feedback energy consumption and throughput with energy efficiency feedback utility (EEFU) function which can adapt to different application scenes by adjusting utilization coefficient. The feedback utilization of two precoders in CoMP systems is analyzed respectively, including the optimization allocation of feedback bits with utility function. The complete EEFU optimized expression and the optimizing flow path satisfying the actual application demands of CoMP systems are then derived. The simulation results illustrate the practicability and necessity of the EEFU function and verify the performance of EEFU with different precoders.

In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

We have taken different set of frequencies and done study of power by varying frequencies and with different SSTL Standard Used for Input/Outputs at fixed temperature i.e. 25 degree Celsius. SSTL family includes SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. Power has been calculated on these standards and analysis has been done to find the standard with least power consumption and to make an energy efficient device. The proposed multiplication algorithm is coded in Verilog, synthesized and simulated using Xilinx ISE design suit 14.2.at the end we can conclude that there can be 34-50% power consumption reduced by using frequency scaling technique and using SSTL Standard used for Input/Output. The maximum power has been consumed by SSTL18_II and minimum power consumption is by SSTL12.

In this work, energy efficient ROM is being designed using Kintex 7 which is able to scale down the circuit to 28 nm. For Testing the ROM compatibility, ROM is operated on operating frequencies (10GHz, 15GHz, 20GHz, 25GHz ) .Whenever capacitance is scaled down from 15pf to 5pf, there is I/O power and total power reduction but it is observed that there is no reduction in Clock power, and a very small reduction in leakage power. FPGA is an Integrated Circuit that comprises of input/output buffer, programmable interconnect structure and an array of configurable logic blocks, which featurisms fast prototyping and consumer configurability which gives the advantage of short turnaround time( i.e. time required from start of process till a functional chip is obtained).10MBits of on chip Memory is being provided on Xilinx FPGA in 36Kbits blocks, which supports dual port operation. Stub Series Terminated Logic (SSTL) is an Input/output standard which is selected because it avoids the transmission lie reflection and overall power dissipation. The purpose of Voltage scaling is to reduce leakage power. When capacitance of output load is scaled from 50pF to 5pF, there are 32-37% saving in I/O Power, 0-0.1% Leakage Power saving, there will be a 1-5% saving in Total Power. This design is implemented on Kintex-7 FPGA using Xilinx ISE & Verilog. The technique of Frequency Scaling has been used to reduce the leakage power consumption within the range of 80% to 44.8%, consumption in total power in range of 45.8% to 21.36% and the reduction in Junction temperature range is from 3.5% to 1.6% for 10GHz frequency.

In this work, we are going to use thermal aware approach in Encoder design and also testing thermal stability by working on different ambient temperatures 298.15K, 308.15K, 318.15K, 328,15K, 338.15K and 348.15K and 358.15K. We have observe the compatibility of our device with wireless network by working on different I/O standards (LVCMOS15 and LVCMOS25) . There is 30.29% reduction in leakage power, when we scale down temperature from 358.15K to 298.15K using LVCMOS15 as I/O standard on 40nm Virtex FPGA. Leakage power is calculated for 65nm FPGA and 90nm FPGA as well .In this work, we are using Verilog Hardware Description Language.

In this work, we are making Energy Efficient Internet of Things (IoTs) Enable RAM. In order to make it energy efficient, we are using low voltage complementary metal oxide semiconductor (LVCMOS) Standards. We are using the 3 different members of LVCMOS IO standards family at different FGPA (virtex-5 and virtex-6) and searching the most energy efficient among them. We are inserting 128-bit IP address in RAM to make internet of things enable RAM. Finally, we are operating our IOTs Enable RAM with different operating frequency of I3, I5, I7, Moto-E and Moto-X.

In this work, our focus is on study and analysis of power and junction temperature at different temperatures and at different capacitance values. Kintex7 is 28-nm FPGA on which we implement our circuit to re-assure power reduction and reduction in junction temperature in sequential circuit. Varying the values of capacitance and temperature enhance the efficiency of the Energy Efficient Traffic Light Controller design. This paper basically deals with FSM (Finite State Machine) and is implemented on FPGA. FGPA is preferred because of its high speed and is inexpensive. Traffic lights are beneficial in managing the traffic, reducing accidents rate, relaxing traffic cop’s job, minimizing fuel consumption and emission and save time. The performance of our energy efficient traffic lights is evaluated and tested through simulations on Xilinx software development kit. For 2.4GHz operating frequency, there is 47.71% reduction in total power dissipation, 69.94% reduction in IOs power dissipation, and 0.78% reduction in junction temperature when we use 28nm FPGA and temperature is 25 degree Celsius and capacitance is scaled down from 100pF to 20pF. For 10GHz operating frequency, there is 54.81% reduction in total power dissipation, 70.11% reduction in IOs power dissipation, 3.52% reduction in leakage power dissipation and 1.92% reduction in junction temperature when we use 28nm FPGA and temperature is 50 degree Celsius and capacitance is scaled down from 100pF to 20pF.

In this paper, we have done analysis of ten different counters in term of frequency related to high performance and power dissipation related to energy efficiency. Conserving energy is now a days a very important aspect. In order to conserve energy consumption of our design, we are using dynamic frequency scaling with default LVCMOS18 IO Standard technique which plays a very important role in power saving. Our design is capable to operate with 1 THz frequency that deliver high performance in less time i.e. 1 pico second. Among 10 different counters, 8 bit simple up counter provide maximum reduction in total power that is 84.25% and 98.33% between a frequency range of 1GHz to 10GHz and 1 GHz to 100 GHz respectively.

This paper incorporates the most efficient layout of the RAM in terms of the power consumption. Various RAM styles have been thoroughly analyzed. Frequency analysis has been done for RAM on 40nm FPGA. The main focus has been on studying the various power consumption parameters (total power, I/O power, signal power and the clock power) at different frequencies for the different layouts. We focus highly to find out the optimum conditions at which the RAM behaves the best. Frequency variations and its effect on the RAM technologies is basically the main point of concern. Lesser the power consumption, more efficiently would the circuit behave because the improvidence in terms of power consumption is reduced. The analysis has been done using the Verilog VHDL language and XILINX 12.1. We lead to a conclusion that the distributed style is the most preferred one and that too at a lower value of frequency. This research would open up many avenues in the field of electronics and communication regarding the design of various energy efficient RAM designs on the FPGA.

In this paper an approach is made to design the voltage based energy efficient mobile charge sensor design and for that reason we have used LVCMOS IO standards. Power dissipation is the major factor that has been analyzed and focused .Voltage sensor is operating at different frequencies and at fix temperature that is 25 degree Celsius. Frequencies of different mobile phones have been evaluated. Frequencies taken in consideration are 1400MHz for Nokia Lumia710, 1.2 GHz for Samsung Galaxy core, 2100 MHz for iphone6, 1700 MHz for HTC/T, 1800 MHz for micromax X091 and 2.2GHz for Song Xperia Z1. This research work, is basically done to check the charging status of a mobile phone. The coding is done in Verilog on 28nm FPGA that is Kintex-7. Kintex7 is 28-nm FPGA on which we implement our circuit to re-assure power reduction and reduction in junction temperature in sequential circuit.There is 4-19% reduction in power dissipation with LVCMOS33, 3-15% reduction in power dissipation with LVCMOS25, 2-13% reduction in power dissipation with LVCMOS18, 2-12% reduction in power dissipation with LVCMOS15, 1-5% reduction in power dissipation with BLVDS25 at 25 degree Celsius when we use 28nm FPGA. The performance of our sensor is evaluated and tested through simulations on Xilinx software development kit. . The quality of our sensor can be improved by changing IO standards.

This paper throws light on the behavior of the UART in response to the variations in the junction temperature. Analysis has been done to find the most ideal temperature range for the operation of the UART. After all the calculations, deduction comes to a point that lowering the temperature values increases the efficiency of the UART significantly since the losses due to the leakage power are reduced to a minimum value when the temperature is decreased. Significant reduction in the percentage of leakage power is seen as the temperature is lowered. Implementation has been done on the FPGA generations Virtex-6, Virtex-5, Virtex-4 using XILINX simulator and Verilog Hardware Description Language. Different reduction percentages have been observed within a range of 8% to 37.4% for the leakage power and 16.8% to 69.3%for the ambient temperature as the results are obtained for frequency values of 1GHz and 1MHz. Thus various power loss parameters have been studied to get the best energy efficient UART.

In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile architecture. For thermal analysis of our energy efficient design, we have taken temperatures of four different regions from reference. Latin Unicode reader takes 16-bit hexadecimal code of alphabet and clock input. At the end we can conclude that the maximum power consumption is at 2.2GHz and minimum power consumption is at 1.2GHz. When we talk in terms of temperature we can see that maximum power is consumed at 329.85K and minimum power is consumed at 294.15K. And also the power dissipation is less in the case of 40nm (Artix-6) and is more in the case of 28nm (Kintex-7). Changing the parameter (Temperature) doesn’t affect the clock power in both cases (Gated and Non-gated).