Earticle

초록

영어

This paper incorporates the most efficient layout of the RAM in terms of the power consumption. Various RAM styles have been thoroughly analyzed. Frequency analysis has been done for RAM on 40nm FPGA. The main focus has been on studying the various power consumption parameters (total power, I/O power, signal power and the clock power) at different frequencies for the different layouts. We focus highly to find out the optimum conditions at which the RAM behaves the best. Frequency variations and its effect on the RAM technologies is basically the main point of concern. Lesser the power consumption, more efficiently would the circuit behave because the improvidence in terms of power consumption is reduced. The analysis has been done using the Verilog VHDL language and XILINX 12.1. We lead to a conclusion that the distributed style is the most preferred one and that too at a lower value of frequency. This research would open up many avenues in the field of electronics and communication regarding the design of various energy efficient RAM designs on the FPGA.

목차

Abstract
 1. Introduction
 2. Related Work
 3. Objective
 4. Results
  4.1 When Device is Operating at 1 GHz
  4.2. When Device is Operating at 10 GHz
  4.3. When Device is Operating at 60 GHz
  4.4. When Device is Operating at 100 GHz
  4.5. When Device is Operating at 1 THz
 5. Conclusion
 6. Future Scopes
 References

키워드

저자

• Rashmi Sharma [ Chitkara University, Chandigarh, India ]
• Lakshay Rohilla [ Chitkara University, Chandigarh, India ]
• Riya Garg [ Chitkara University, Chandigarh, India ]
• Aman Sharma [ Chitkara University, Chandigarh, India ]
• Sweety Dabbas [ Maharaja Surajmal Institute, Janakpuri, Delhi ]
• Akhil Nibber [ Chitkara University, Chandigarh, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605