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HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

첫 페이지 보기
  • 발행기관
    보안공학연구지원센터(IJCA) 바로가기
  • 간행물
    International Journal of Control and Automation SCOPUS 바로가기
  • 통권
    Vol.8 No.8 (2015.08)바로가기
  • 페이지
    pp.35-44
  • 저자
    Shivani Madhok, Bishwajeet Pandey, Amanpreet Kaur, Mohamed Hashim Minver, D M Akbar Hussain
  • 언어
    영어(ENG)
  • URL
    https://www.earticle.net/Article/A253901

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원문정보

초록

영어
In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

목차

Abstract
 1. Introduction
 2. Power Analysis
  A. Power Analysis for HSTL_I IO STANDARD
  B. Power Analysis for HSTL_II IO STANDARD
  C. Power Analysis for HSTL_I_18 IO STANDARD
  D. Power Analysis for HSTL_II_18 IO STANDARD
  E. Power Analysis for HSTL_I_12 IO STANDARD
  F. Power Analysis for Different IO Standard with Different Frequencies
 3. Conclusion
 4. Future Scope
 References

키워드

Nikhilam Navatashcaramam Dashatah Vedic mathematics FPGA energy efficient multiplier

저자

  • Shivani Madhok [ Chitkara University Research and Innovation Network Chitkara University Chandigarh, Punjab ]
  • Bishwajeet Pandey [ Chitkara University Research and Innovation Network Chitkara University Chandigarh, Punjab ]
  • Amanpreet Kaur [ Chitkara University Research and Innovation Network Chitkara University Chandigarh, Punjab ]
  • Mohamed Hashim Minver [ Addalaichenai National College of Education, Sri Lanka ]
  • D M Akbar Hussain [ Department of Energy Technology Aalborg University, Denmark ]

참고문헌

자료제공 : 네이버학술정보

간행물 정보

발행기관

  • 발행기관명
    보안공학연구지원센터(IJCA) [Science & Engineering Research Support Center, Republic of Korea(IJCA)]
  • 설립연도
    2006
  • 분야
    공학>컴퓨터학
  • 소개
    1. 보안공학에 대한 각종 조사 및 연구 2. 보안공학에 대한 응용기술 연구 및 발표 3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최 4. 보안공학 기술의 상호 협조 및 정보교환 5. 보안공학에 관한 표준화 사업 및 규격의 제정 6. 보안공학에 관한 산학연 협동의 증진 7. 국제적 학술 교류 및 기술 협력 8. 보안공학에 관한 논문지 발간 9. 기타 본 회 목적 달성에 필요한 사업

간행물

  • 간행물명
    International Journal of Control and Automation
  • 간기
    월간
  • pISSN
    2005-4297
  • 수록기간
    2008~2016
  • 십진분류
    KDC 505 DDC 605

이 권호 내 다른 논문 / International Journal of Control and Automation Vol.8 No.8

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