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Dilithium was selected as one of NIST standard Post Quantum Digital Signature algorithms and is undergoing standardization as a Module Lattice Digital Signature Algorithm (ML-DSA). However, until now research on optimization in embedded environments has primarily been conducted on ARM architectures, which are the basic benchmark targets. To prepare for future quantum secure Internet of Things environments, performance optimization on resource-constrained must be considered. Thus, in this paper, for the first time, we propose an optimized implementation of Dilithium in the 16-bit MSP430 environment, a low-resource device. We redesign the state-of-the-art optimization strategies for Dilithium to suit the MSP430 environment. By taking full advantage of MSP430’s hardware multiplier in the NTT-based polynomial multiplication, we achieve 73.0% and 80.1% of performance improvement for NTT and NTT?1 compared to those in the reference implementation, which contributes about 5.5%?7.0%, 15.3%?17.5%, and 7.5%?10.0% of performance improvement compared to Dilithium’s public reference implementation for keypair generation, signing, and verification, respectively.

Background/Objectives: This paper presents the hardware implementation of SpoC Lightweight Cryptography (LWC) candidate for low-cost devices. Methods/Statistical analysis: The proposed hardware implementation of the SpoC Authenticated Encryption with Associated Data (AEAD) is capable of both encryption and decryption. The design was implemented on the Virtex-4 Field FPGA using Xilinx ISE Design Suite. The synthesis results reported 951 slices at 246.61 MHz maximum clock frequency. The encryption and decryption routines take 589 and 590 cycles. Findings: This work used 30% fewer LUTs for both encryption and decryption as compared to the existing work. The decrease in area in this work is a result of the optimization of the implementation for low-cost devices while the existing work implemented the basic iterative architecture without optimizing. This work achieved almost two times the frequency of the existing SpoC implementation. The existing SpoC implementation used 150 fewer cycles as compared to this work. This is because this work implemented the SpoC using extra registers in other to reduce the critical path which increases the frequency. Improvements/Applications: For future works, the proposed SpoC AEAD will be combined with other security protocols to form a lightweight cryptographic System-on-Chip (SoC).

Due to the recent improvement in the computational power of hardware and the growth of data, a deep learning-based approach that optimizes parameters using massive data showed excellent performance. In computer vision, research using a convolutional neural network(CNN) is being actively conducted. However, it is challenging to apply to IoT devices due to the high computational complexity and massive memory usage required. In this paper, we propose a quantized CNN hardware for IoT devices that optimized memory usage and computation complexity. In addition, we present a quantization framework for the proposed hardware design. The presented framework includes floating-point training, quantization, fully integer arithmetic inference, and hardware design processes. As a result of implementing the quantized CNN on the Xilinx ZC702 evaluation board, power consumption and inference speed improved by 4.86× and 2.58×, respectively, compared to 32-bit floating-point hardware.

최근 들어, 스마트 단말에서 지불, 인터넷 뱅킹 등 금융업무와 관련된 중요한 정보들을 다루는 경우가 많 아졌다. 또한 스마트 단말의 실행환경이 공개 소프트웨어 환경 위주로 발전하면서, 사용자들이 임의의 응용소프트웨 어를 다운받아 사용하는 것이 용이하게 됨에 따라, 스마트 단말이 보안적 측면에서 취약하게 되었다. 본 논문에서는 하드웨어 기반의 스마트 단말 보안 기술의 특징을 알아본다. 또한, 본 논문에서는 스마트 단말 에서 실행되는 응용 프로그램을 위한 MTM 하드웨어기반의 안전한 스마트 단말 실행환경에 대한 구현방법을 제안한다. 기존의 MTM 이 모바일 장치에 대한 신뢰의 근원 기능만을 제공한 반면, 본 논문에서 제시하는 MTM 기반 모바일 보안 환경은 모바 일 장치에서 실행되는 응용프로그램이 필요로 하는 다양한 보안 기능을 제공할 수 있다. 향후, 보안 하드웨어와 연 동이 가능한 IoT 기기와 게이트웨이 보안 기술, 그리고 보안 하드웨어를 활용하여 다양한 IoT 기기에 적용하여 신뢰 성과 보안성을 확보하는 방안에 대한 연구를 진행할 예정이다.

Recently, the frequency of dealing important information regarding financial services like paying through smart device or internet banking on smart device has been increasing. Also, with the development of smart device execution environment towards open software environment, it became easier for users to download and use random application software, and its security aspect appears to be weakening. This study inspects features of hardware-based smart device security technology. Furthermore, this study proposes a realization method in MTM hardware-based secure smart device execution environment for an application software that runs in smart devices. While existing MTM provides the root of trust function only for the mobile device, the MTM-based mobile security environment technology proposed in this paper can provide numerous security functions that application program needs in mobile device. The further researches on IoT devices that are compatible with security hardware, gateway security technology and methods that secure reliability and security applicable to varied IoT devices by advancing security hardware are the next plan to proceed.

수많은 기기들이 연결된 사물인터넷에서 기기들이 서로를 식별하고 상호작용하기 위해서는 보안이 매우 중요하다. 최근 많은 관심을 받는 물리적 복제 불가 함수(PUF: Physical unclonable function)는 생산 공정에서 물리적으로 발생하는 개체 간 편차를 이용하는 하드웨어 기반 보안 기술이다. 이 논문은 strong PUF의 정의, 실제 구현 방법, 최근 이슈가 되는 기계학습 공격과 그 대안을 다룬다. PUF의 동작 원리와 관련 연구 등 배경 지식을 소개하고, PUF의 유형을 weak PUF와 strong PUF로 구분하여 본질적인 차이점과 활용 분야를 명확히 한다. 단 순 arbiter PUF에서 최근 비선형 기법을 조합한 PUF의 프로토타입에 이르기까지, 다양한 strong PUF의 연구 동 향과 흐름을 다룸으로써 실제 PUF 회로 구현 방법을 제시한다. 대표적 PUF 성능 평가 지표인 유일성와 신뢰도를 수식으로 정리하고, 기계학습 공격 저항을 자세히 설명하여 관련 이슈의 최근 흐름과 향후 연구 방향을 제시한다.

Security is one of the most important issues in Internet of Things where billions of interconnected devices identify and interact with each other. Physical unclonable function (PUF) attracts lots of research interest as a strong security technology. It is a hardware-based security utilizing physical deviation among devices resulted from silicon manufacturing process. In this paper, we address definition of strong PUF, practical implementation, issues and countermeasures on machine learning attacks. A brief introduction on PUF basics and related works are presented, and followed by the definitions of strong and weak PUFs to clarify the difference of the two categories and their applications. With various types of strong PUFs from the simple arbiter PUF to recent PUF prototypes elaborated, we propose a practical implementation. For the purpose of performance evaluation, uniqueness and reliability are explained with mathematic expressions and machine learning (ML) attack resistance is introduced. We also present threat and countermeasure of ML attacks.

본 논문에서 오픈 소스 하드웨어인 아두이노 기반의 스마트 온실관리 시스템 모델을 제안하고 구현하였다. 제안된 스마트 온실관리 시스템은 센서 및 아두이노 등으로 구성된 제어 장치부, 온실 제어를 담당하는 에이전트 (Agent) 프로그램, 사용자 API를 담당하는 웹 어플리케이션 등으로 구성되어 있다. 제어장치부는 온도, 습도, 광조, 수분 센서 데이터를 에이전트 프로그램으로 전송하고, 에이전트 프로그램은 데이터를 DB에 저장하거나 사용자의 제어 값을 제어장치부에 전송한다. 사용자는 웹을 통해 온실의 센싱 정보를 확인하거나 각종 액츄에이터 (Actuator)를 원격 제어할 수 있다. 또한 제안 시스템의 상황 인지 및 자율 제어 기능을 통해 스마트한 온실 관리가 가능하다. 구현 결과, 제안된 온실관리 시스템 모델이 잘 동작함을 확인할 수 있었다.

In this paper, we proposed an arduino-based smart green house management system model and implemented it. The proposed system consists of control unit composed of sensors and arduino, agent program controlling the green house, and web applications providing user interfaces. The control unit transmits data of sensors such as temperature, humidity, illuminance, moisture, etc. to the agent program, and then the agent saves the data in its database. In reverse, control data are transmitted from agent program to control unit. Users can monitor sensed data of green houses and control actuators remotely using web. Plus, smart green house management is available by context awareness and autonomous control functions of the proposed system.

To the existing real-time operating systems implemented by software, it is hard to continually enhance their real-time performance by simply improving their scheduling algorithms. New scheduling algorithms of μC/OS-II real-time operating systems and their hardware implementation are shown in this paper. They breakthrough the limit of the number of total task, and hardware task scheduler was used to select tasks from ready list instead of the original ready table, improving the efficiency and maintaining the correctness of the real-time system. This system design adopted VHDL hardware description language and implemented and simulated in ISE 8.2. Based on the result, new task scheduling algorithms and hardware scheduler decrease the cost of hardware logic and spending of running time, while the new task management and TCB data structure keep the correctness of the original software version.

Integer Discrete Cosine Transform (DCT) is among the techniques used to improve the performance of the H.264/AVC Standard. All the profiles in the H.264/AVC standard support 4×4 integer DCT and the high profiles of this standard support 8×8 integer DCT as well as the 4×4 integer DCT. Various hardware realizations have been proposed for forward and inverse integer DCT in the literature because they are among the computational intensive units in the H.264/AVC standard. In this paper we propose a unified pipelined architecture to realize of the entire forward and inverse DCTs as well as the Hadamard transforms in the H.264/AVC encoder. The synthesis results indicate that our architecture achieves higher clock rate and relatively lower gate count compared to the other published architectures that realize only a number of the transforms in the H.264/AVC encoder.

Aiming at the problem that μC/OS-II does not support round-robin scheduling of the same priority task, a two-level hybrid task scheduling strategy was proposed. In the first level, by putting the task priority as criterion for task scheduling, a preemptive scheduling of different priority task was implemented. And in the second level, adopting time slice circulars scheduling strategy, round-robin scheduling of same priority task was implemented. The waiting list of tasks was designed by on-chip registers of FPGA and the ready list of tasks was designed by RAM of FPGA, and to implement time slice circulars scheduling, hardware circuit for finding successor of task was designed. The system adopted VHDL, and simulated by the software ISE10.1. The simulation results show that the hardware implementation of the system is well-worked.

Sea-skimming missiles fly at very low altitude (5m-10m) above the mean sea level. An altimeter based height control system is used to keep the missile at the desired height by measuring the instantaneous height of the missile above the sea level. The altimeter measurement comes with the disturbances which forces the missile to follow the sea waves resulting is a complex trajectory and high energy requirements. An extended state observer based height control system with a proportional derivative controller is used for the real time estimation and rejection of sea wave disturbances to achieve a stable flight path for the missile. Simulations are carried out in both continuous and digital domain to understand the hardware implementation imperatives of the same.

Implementing an algorithm into hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated into a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, because the designer must take care of low-level details, and write test benches to test the implementation’s behaviour. This paper presents a global design method, from high level description to implementation. The first step consists of the description of an algorithm as a dataflow program using RVC-CAL language. The next step is the functional verification of this description using a software framework. The final step consists of an automatic generation of an efficient hardware implementation from the dataflow program. The objective is to spend the greater part of the conception time in an open source software platform. We use this method to quickly prototype and generate hardware implementation of a baseline part of the LAR coder, from an RVC-CAL description.

We present a shape recognition scheme for real-time embedded systems. It was hard to achieve real-time processing on the typical embedded systems. After analyzing the overall image processing and shape recognition process, we introduced massively parallel processing schemes, and finally implemented special purpose FPGA chips. Strengthen with this FPGA implementation, our target board achieved real-time shape recognition. A two-leg walking robot was directed to the target positions after the shape recognition, for demonstration purpose. We will extend these real-time shape recognition schemes for other image processing applications.

This paper presents a finite element model-based real-time simulation system for the permanent magnet synchronous motor (PMSM) driving system, which, in combination with the vehicle kinetic model, forms a complete electric vehicle (EV) hardware-in-the-loop (HIL) simulation and test platform. The software JMAG is used to establish the PMSM finite element model, and the platform of field-programmable gate array (FPGA) is adopted to construct the PMSM real-time simulation model. The finite element model is also retrieved to coordinate with the vehicle kinetic model in order to facilitate the testing and development of the controller of the EV, the matching of the driving system, the kinetics control algorithms, etc. Through comparing the real-time simulation of the motor driving system with the experimental results of the test bench, as well as analyzing the HIL simulation results of the entire vehicle model, this paper verifies the accuracy and effectiveness of this HIL simulation and test platform.

Self-validating (SEVA) pneumatic actuator is a new generation of actuator which can not only give the corresponding output according to the input control variable but also give the accuracy of the control output and status of the actuator itself and other information. A dual processor system is implemented using C8051F060 and TMS320F28335 to acquire the signals and complete fault detection, diagnosis and self-validating parameters calculating. C8051F060 is used to data acquisition and preprocessing of the actuator inner signals, and communicate with Host PC.TMS320F28335 is used to run the self-validation algorithm and fault diagnosis algorithm and transfer the self-validation outputs to C8051F060. Experimental results indicate that the sell-validating unit can acquire the actuator inner sensors data correctly in normal state and fault state. With software modification of DSP and MCU, the system can be used in data acquisition and signal processing for other actuators.

Nowadays, as the availability of tiny, low-cost microcomputer increases at a high level, mobile robots are experiencing remarkable enhancements in hardware design, software performance, and connectivity advancements. In order to control Turtlebot 2, several algorithms have been developed using the Robot Operating System(ROS). However, ROS requires to be run on a high-cost computer which increases the hardware cost and the power consumption to the robot. Therefore, design an algorithm based on low-cost hardware is the most innovative way to reduce the unnecessary costs of the hardware, to increase the performance, and to decrease the power consumed by the computer on the robot. In this paper, we present a path-finding algorithm for TurtleBot 2 based on low-cost hardware. We implemented the algorithm using Raspberry pi, Windows 10 IoT core, and RPLIDAR A2. Firstly, we used Raspberry pi as the alternative to the computer employed to handle ROS and to control the robot. Raspberry pi has the advantages of reducing the hardware cost and the energy consumed by the computer on the robot. Secondly, using RPLIDAR A2 and Windows 10 IoT core which is running on Raspberry pi, we implemented the path-finding algorithm which allows TurtleBot 2 to navigate from the starting point to the destination using the map of the area. In addition, we used C# and Universal Windows Platform to implement the proposed algorithm.

본 논문에서는 차량용 네트워크인 CAN(controller area network)와 연계되어 다양한 안전진단을 가능하게 하는 안전진단 센서하드웨어를 구현하고 그 성능을 확인하였다. 본 연구를 통하여 새롭게 설계 및 구현된 안전진단센서 하드웨어는 차량용 CAN인터페이스와 연결되며, 안전진단을 위한 다양한 센서(충돌센서, 거리 센서 등)의 데이터를 취득하고 이를 처리하여 CAN, RS232, RS485, I2C등의 통신인터페이스를 통해 전송하는 구조를 가지고 있다. 본 논문에서는 새롭게 설계 제작된 CAN연계형 안전진단 센서보드의 동작을 센싱 데이터와 연계하여 다양한 상황에서 그 성능을 검증함으로서 개발된 하드웨어의 유용성을 확인하였다.

This paper is a study of Car safety network system using sensed data from varied sensors. This hardware will work with various sensors and communication protocols. There are many sensors. Then, I selected 3 sensors for test, which were sonic sensor for distance checking, tilt sensor for rollover and impact sensor for car accident and theft. Also, there are many interfaces for sensor. Therefore I designed hardware to support various sensor interfaces. For instance ADC(Analog to Digital converter), I2C, RS232, RS485, CAN. In this case, sonic sensor have I2C interface, tilt sensor have RS485 interface and Impact sensor have analog interface. In this research, I can gather sensing data from 3 sensors (mentioned above), and sending control signal to other processor with RS232, RS485, CAN communication. So, we can use easily this hardware for many cases of systems, which need sensors.

본 논문에서 오픈 소스 하드웨어인 아두이노를 기반으로 하는 스마트 센서 네트워크 시스템 모델을 제안하고 구현하였다. 제안된 스마트 센서 네트워크 시스템은 센서 및 센서의 값을 처리할 수 있는 오픈 소스 하드웨어 기반인 아두이노 등으로 구성된다. 또한 센서로 부터 측정된 센서값을 활용할 수 있는 제어 장치부에 전송할 통신 모듈도 구 성하였다. 제어 장치부에서는 온도, 습도, 광량과 같은 센서 데이터를 메인 프로그램으로 전송하고 메인 프로그램은 데 이터를 DB에 저장하거나 특정한 제어 신호의 값을 제어장치 혹은 엑츄에이터에 전송한다. 사용자는 또한 웹을 통해 스마트 센서 네트워크에서 측정된 값을 사용하는 시스템의 정보를 확인하거나 각종 액츄에이터를 원격 제어할 수 있으 며 제안 시스템의 상황 인지 및 자율 제어 기능을 통해 스마트한 관리가 가능하다.

In this paper, we have proposed and implemented a smart sensor network system based on the Arduino open source hardware. The proposed smart sensor network system is composed of kinds of sensors and open- source hardware based, Arduino, etc. that can handle the measured sensor values. Also the communication modules that can be used to transmit the measured sensor values from the sensor control unit are configured. In the control unit the sensor data such as temperature, humidity, light intensity can be transmit to the main program and the main program will save the data in the DB or transmitting the value of the particular control signal to the control device or the actuator. The user can also check the information in the system using the measured values from the smart sensor networks through the web, or to remotely control a variety of actuators. And it is possible to manage a smart autonomous control over whether and how the proposed system.

Solar photovoltaic systems have evolved as a prominent renewable source of energy owing to its eco-friendly nature, long lifetime, and low maintenance requirement. However, its conversion efficiency is very low. Different maximum power point tracking (MPPT) techniques have been used to extract maximum power from the photovoltaic system. In this study, the perturb and observe (P&O) MPPT algorithm, which is practically implemented on an Arduino Uno board and simulated in Matlab/Simulink under the same environmental conditions, is used to track the maximum power. Different parameters of a Simulink-based PV module and a practical photovoltaic module are obtained and compared. The main advantages of the P&O MPPT algorithm are its low cost and easy implementation. However, it may fail to track the maximum operating point under varying environmental conditions.

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.