Earticle

Broadcasting system in the world has been changing rapidly analog into digital and most of the countries have plan to shutdown the analog system. Digital system has a high efficiency of bandwidth because it can easily do data compression. Service is being diversified and increased requirements of the data quality. In this reason data protection from hacker is most important for contents and data delivery system. In the broadcasting field, we called CAS system widely adopted for encryption and decryption of data and contents. Also, digital stream should be stored in the terminal for easy playback at once. DVR(Digital Video Recorder) is one of the important components of the broadcasting and IPTV terminals.

This paper proposes high-speed computing decoders for polar codes based on a neural network. To compensate for the performance gap with the successive cancellation decoder, we propose applying the recurrent neural network to the BP decoder with a modified factor graph to reduce the computational complexity of the decoder without any performance degradation. The results of the performance simulation conducted in this paper reveal that the proposed decoder requires substantially less computational complexity than the conventional decoders to achieve the same bit error rate performance.

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

This paper introduces an efficient non-binary low-density parity-check (NB-LDPC) decoder architecture, in terms of increasing decoding throughput. By taking advantages of non-binary quasi-cyclic LDPC codes, a new layered decoding algorithm and corresponding efficient hardware architecture are introduced. The proposed method can improve parallelism in decoding estimations of NB-LDPC decoder while remaining error-correcting performance. The implementations results confirmed that the proposed decoder with two threads can achieve a throughput of about 2.78 Gbps, which is around 1.63 times faster than that of the state-of-the-art decoder at almost the same hardware efficiency.

네트워크의 성능 향상을 위해 제안된 네트워크 코딩은 P2P 시스템과 같은 멀티캐스팅 네트워크의 성능을 향상 시킨다고 알려져 있다. 네트워크 코딩 기법은 발신지와 목적지 사이의 중간 노드들에서 부호화 작업이 이루어지고, 목적지 노드에서는 여러 단계를 거쳐 부호화된 데이터를 전달 받기 때문에 발신 노드가 보낸 실제 정보를 얻기 위해서 복호화 과정을 거쳐야 하므로 복호화 연산의 성능은 전체 네트워크의 성능에 영향을 미치게 된다. 본 연구에서 복호화 과정에 필요한 갈로아 유한체에서의 가우스 소거법 연산을 FPGA(Field Programmable Gate Array)를 이용한 HW기반 가속화 시스템을 구현하였다. 논문에서는 하드웨어 구현에 있어 병렬처리, 파이프라인 데이터 처리 등의 이슈에 대해 논하고, 그 성능을 범용 시스템 상에서 SW로 수행하는 경우와 비교하였다. FPGA를 활용하여 복호화 전용 가속기능을 구현할 경우, Pentium 4 기반의 범용 시스템과 비교해서 20배, ARM기반 임베디드 시스템에 비해서는 140배 이상의 성능향상을 보였으며, 이를 활용할 경우 소규모의 연산 자원을 이용해서 효율적인 네트워크 코딩 시스템을 구현할 수 있을 것으로 기대된다.

Network Coding enhances performance of multi-cast network system, e.g., P2P(Peer-to-Peer) system. The Receivers in the network that use network coding technique have to decode the received messages which are encoded by intermediate nodes as well as sender node. Hence, decoding operations of network coding system are more complex than those of normal network system; therefore, performance of decoding operations have a significant influence on performance of the entire network system. In this paper, we address the issues regarding implementation of FPGA-based acceleration engines of Gaussian eliminations on finite Galois field. We compare the decoding performance on FPGAs with SW based implementations on P-4 processor and ARM embedded processor. The result shows that FPGA implementation outperforms contemporary widespread P-4 processor and ARM processors by 20 and 140 times, respectively. Utilizing the technique introduced in this paper, an efficient network coding system could be realized with a low level of computing resources.

지금까지 오랜 시간 동안 범용 프로세서는 개발자에게 버그 수정을 할 수 있는 도구들을 제공하기 위해 전용 하드웨어/소 프트웨어 트레이싱 모듈을 제공했다. 전용 하드웨어 트레이서는 성능 분석 및 디버깅에 모두 사용되는 막대한 양의 데이터를 로그로 실시간으로 생성한다. 프로세서 트레이스 (PT)는 CPU에서 실행되는 분기를 추적하는 Intel CPU를 위한 새로운 하드 웨어 기반 추적 기능으로 최소한의 노력으로 모든 실행 코드의 제어 흐름을 재구성할 수 있다. 이러한 하드웨어 트레이스 기 능들은 운영체제에 통합되어 프로파일 링 및 디버깅 메커니즘과의 긴밀한 통합이 가능하게 되었다. 본 논문에서는 윈도우 환 경에서 PT가 제공하는 기능을 이용하여 실시간 트레이스 및 악성코드 검출을 위한 기본 데이터를 제공하는 확장된 PT 디코 더 구조를 제안하였다.

For a long time now, general-purpose processors have provided dedicated hardware / software tracing modules to provi de developers with tools to fix bugs. A hardware tracer generates its enormous data into a log that is used for both perfo rmance analysis and debugging. Processor Trace (PT) is a new hardware-based tracing feature for Intel CPUs that traces branches executing on the CPU, which allows the reconstruction of the control flow of all executed code with minimal lab or. Hardware tracer has been integrated into the operating system, which allows tight integration with its profiling and de bugging mechanisms. However, in the Windows environment, existing studies related to PT focused on decoding only one flow in sequence. In this paper, we propose an extended PT decoder structure that provides basic data for real-time trace and malicious code detection using the functions provided by PT in Windows environment.

본 논문에서는 인코더-디코더 모델(encoder-decoder model)에서 잠재 벡터(latent vector)의 분류 성능을 비교 분석한다. 오토인코더와 같은 일반적인 인코더-디코더 모델은 인코더 입력을 잠재 벡터로 변환하고 이를 디코더에 입력하여 인코더 입력과 유사한 출력을 생성하도록 학습한다. 이와 같은 인코더-디코더 모델의 잠재 벡터는 인코더 입력의 특징을 추상화하여 잘 보존한다고 고려할 수 있다. 나아가 잠재 벡터가 특징 공간에서 클러스터들 사이에서 구분이 가능한 거리를 보장한다면 이를 비지도 학습에 적용하는 것이 가능하다. 본 논문에서는 인코더-디코더 모델 에서의 잠재 벡터를 비지도 학습 및 점진적 학습에 적용하기 위한 기초 연구로서 잠재 벡터의 분류 성능을 분석한 다. 이를 위해 스택트 오토인코더(stacked autoencoder)와 2가지 종류의 CNN(Convolutional Neural Network) 기반 오토인코더를 바탕으로 각각 구해지는 잠재 벡터를 KNN(K-Nearest Neighbor)과 랜덤 포레스 트(random forest)를 포함하는 4가지 종류의 분류기에 적용한다. 실험 결과 완전 연결 계층(fully connected or dense layer)를 가지는 CNN 기반의 오토인코더를 사용한 결과 평균 정확률은 약 97%이고 스택트 오토인코더의 결과는 약 95%로 2% 정도 우수한 분류 성능을 보이는 것을 확인할 수 있다. 본 논문에서의 연구를 바탕으로 완전 연결 계층을 가지는 CNN 기반의 오토 인코더를 이용하여 구해지는 잠재 벡터를 비지도 학습에 적용하는 것으로 확 장하는 것이 가능하다.

This paper compares and analyzes the classification performance of latent vectors in the encoder-decoder model. A typical encoder-decoder model, such as an autoencoder, transforms the encoder input into a latent vector and feeds it into the decoder. In this process, the encoderdecoder model learns to produce an decoder output similar to the encoder input. We can consider that the latent vector of the encoder-decoder model is well preserved by abstracting the characteristics of the encoder input. Further, it is possible to apply to unsupervised learning, if the latent vector guarantees a sufficient distance between clusters in the feature space. In this paper, the classification performance of latent vectors is analyzed as a basic study for applying latent vectors in encoder-decoder models to unsupervised and continual learning. The latent vectors obtained by the stacked autoencoder and 2 types of CNN-based autoencoder are applied to 4 kinds of classifiers including KNN and random forest. Experimental results show that the latent vector using the CNN-based autoencoder with a dense layer(about 97%) shows superior classification performance by up to 2% compared to the result of the stacked autoencoder(about 95%). Based on the results in this paper, it is possible to extend the latent vector obtained by using a CNN-based auto-encoder with dense layer to unsupervised learning.

소프트웨어 공학 관점에서 트레이싱은 프로그램의 실행 정보를 기록하는 로깅의 특수한 형태이다. 엄청난 데이터를 실시간 으로 생성하고 디코딩해야 하는 트레이서의 특징상 전용 하드웨어를 사용하는 트레이서가 많이 사용되고 있다. Intel® PT는 전용 하드웨어를 사용하여 각 하드웨어 쓰레드에서 소프트웨어 실행에 대한 모든 정보를 기록한다. 소프트웨어 실행이 완료되 면 PT는 해당 소프트웨어의 트레이스 데이터를 처리하여 정확한 프로그램 흐름을 재구성할 수 있다. 하드웨어 트레이스 프로 그램은 운영체제에 통합되어 사용할 수 있으나 윈도우 시스템의 경우에는 커널 개방과 같은 문제로 인하여 긴밀한 통합은 이 루어지지 않고 있다. 또한, 단일 프로세스만 트레이스 할 수 있고 다중 프로세스 스트림을 트레이스 하는 방법은 제공하고 있 지 않다. 본 논문에서는 이러한 단점을 극복하고자 윈도우 환경에서 다중 프로세스 스트림을 트레이스 지원이 가능하도록 기 존의 PT 트레이스 프로그램을 확장하는 방안을 제안하였다.

From a software engineering point of view, tracing is a special form of logging that records program execution informa tion. Tracers using dedicated hardware are often used because of the characteristics of tracers that need to generate and d ecode huge amounts of data in real time. Intel® PT uses proprietary hardware to record all information about software ex ecution on each hardware thread. When the software execution is completed, the PT can process the trace data of the soft ware and reconstruct the correct program flow. The hardware trace program can be integrated into the operating system, but in the case of the window system, the integration is not tight due to problems such as the kernel opening. Also, it is possible to trace only a single process and not provide a way to trace multiple process streams. In this paper, we propose a method to extend existing PT trace program to support multi - process stream traceability in Windows environment in order to overcome these disadvantages.

빅데이터 시대를 맞이하여 인공지능 분야는 괄목할만한 성장을 보이고 있으며 특히 딥러닝에 의한 이미지 분류 학습방법이 중요한 영역으로 자리하고 있다. 이미지 분류에서 많이 사용되어 온 CNN의 성능을 더욱 개선하기 위해 다양한 연구가 활발하게 진행되었는데, 이 중에서 대표적인 방법이 CRNN(Convolutional Recurrent Neural Network) 알고리즘이다. CRNN 알고리즘은 이미지 분류를 위한 CNN과 시계열적 요소를 인식하기 위한 RNN의 조합으로 구성되는데, CRNN의 RNN영역에서 사용하는 입력값은 학습 대상의 이미지를 합성곱과 풀링 기법을 적용하여 추출된 결과물을 flatten한 값이고, 이 입력값들은 이미지 내 동일 위상에 있는 픽셀값들이 서로 다른 순서로 나타나기 때문에, RNN에서 의도한 이미지 내 배열 순서를 제대로 학습하기 어렵다는 한계점을 지닌다. 따라서 본 연구는 인코더와 디코더의 개념을 응용한 CNN과 RNN의 새로운 하이브리드 방법을 제안하여, 이미지 분류 성능을 향상시키는 것을 목적으로 하였다. 본 연구에서는 다양한 알고리즘 비교 실험을 통해, 새로운 하이브리드 방법의 효과성을 검증하였다. 본 연구는 인코더와 디코더 개념의 적용 가능성을 넓히고, 제안한 방법이 기존 하이브리드 방법에 비해, 복잡도가 크게 증가하지 않아 모델 학습 시간과 인프라 구축 비용 측면에서 이점을 있다는 점에서 학문적 시사점을 가진다. 또한, 정확한 이미지 분류가 필요한 다양한 분야에서 제공되는 서비스의 품질을 높일 수 있는 가능성을 제시하였다는 점에서 실무적 시사점을 가진다.

In the era of big data, the field of artificial intelligence is showing remarkable growth, and in particular, the image classification learning methods by deep learning are becoming an important area. Various studies have been actively conducted to further improve the performance of CNNs, which have been widely used in image classification, among which a representative method is the Convolutional Recurrent Neural Network (CRNN) algorithm. The CRNN algorithm consists of a combination of CNN for image classification and RNNs for recognizing time series elements. However, since the inputs used in the RNN area of CRNN are the flatten values extracted by applying the convolution and pooling technique to the image, pixel values in the same phase in the image appear in different order. And this makes it difficult to properly learn the sequence of arrangements in the image intended by the RNN. Therefore, this study aims to improve image classification performance by proposing a novel hybrid method of CNN and RNN applying the concepts of encoder and decoder. In this study, the effectiveness of the new hybrid method was verified through various experiments. This study has academic implications in that it broadens the applicability of encoder and decoder concepts, and the proposed method has advantages in terms of model learning time and infrastructure construction costs as it does not significantly increase complexity compared to conventional hybrid methods. In addition, this study has practical implications in that it presents the possibility of improving the quality of services provided in various fields that require accurate image classification.

Speech is the most natural communication mode for human beings. The task of speech recognition is to convert speech into a sequence of words by a computer program. Speech recognition applications enable people to use speech as another input mode to interact with applications with ease and effectively. Speech recognition interfaces in native language will enable the illiterate/semi-literate people to use the technology to greater extent without the knowledge of operating with computer keyboard or stylus. For more than three decades, a great amount of research was carried out on various aspects of speech recognition and its applications. Today many products have been developed that successfully utilize automatic speech recognition for communication between human and machines. Performance of speech recognition applications deteriorates in the presence of reverberation and even low levels of ambient noise. Robustness to noise, reverberation and characteristics of the transducer is still an unsolved problem that makes the research in the area of speech recognition still very active. A detailed study on automatic speech recognition is carried out and presented in this paper that covers the architecture, speech parameterization, methodologies, characteristics, issues, databases, tools and applications.

This paper presents a quantum-dot cellular automata (QCA) 3-8 decoder with low hardware complexity. The proposed architecture is based on inverter chains to get inverse value and cross over a wire. We also use 5-input majority voting gates for 3-input AND gates. In this paper, we focus on the hardware complexity to reduce the number of cells and minimize wasting an area. Our architecture has not only an excellent regularity and scalability but a strong signal strength so that it is easy to extend a structure and connect with other circuit.

Quantum-dot cellular automata(QCA) provides a new approach in computer circuit design and development at nanotechnology level. This technology promises extraordinary high computing speeds, low heat dissipation and highly dense circuits. In this paper,two 2:4 decodersare proposed. The proposed structures reduce the clock phases to only three phases making them faster than the designs currently available in literature.The first proposed structure has reduced number of cells and hence covers a small area.The second proposed method although it has more cells, has regular clock zones that can facilitate the implementation of this circuit.Simulation of the circuits was done using QCADesigner.

Low Density Parity Check codes are FEC codes and consequently data rate is more. They are linear error correcting codes for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance, Low Decoding Complexity. The main advantage of the parity check matrix is the decoder can correct all single-bit errors. In this Paper LDPC encoder and decoder architecture for coding 3-bit message vector will be analyzed and also designed using VHDL.

By using MATLAB, a kind of software decoder is designed which has filter and fault correction function and is used in aviation radio communication. Through Morse code text, using dits and dashes to uniquely represent characters such as alphabets、numbers and punctuations (41), those characters are coded through algorithm. A new decoding algorithm is designed which is composed of filtration, binary, difference and zero removal operation. This decoding method is robust and interference immunity, it also has such functions as filtering and fault correction. It can filter the random noise and Gaussian noise so as to reduce the error rate of aviation radio communication and thereby increase the quality of aviation radio communication. This method is checked though an example to decode the word “Hello”.