Earticle

초록

영어

This paper introduces an efficient non-binary low-density parity-check (NB-LDPC) decoder architecture, in terms of increasing decoding throughput. By taking advantages of non-binary quasi-cyclic LDPC codes, a new layered decoding algorithm and corresponding efficient hardware architecture are introduced. The proposed method can improve parallelism in decoding estimations of NB-LDPC decoder while remaining error-correcting performance. The implementations results confirmed that the proposed decoder with two threads can achieve a throughput of about 2.78 Gbps, which is around 1.63 times faster than that of the state-of-the-art decoder at almost the same hardware efficiency.

목차

Abstract
I. INTRODUCTION
II. NB-LDPC LAYERED DECODING ALGORITHM
III. PROPOSED MULTI-THREADED NB-LDPC DECODER
A. Multi-threaded NB-LDPC algorithm
B. Proposed two-threaded NB-LDPC decoder architecture
IV. IMPLEMENTATION RESULTS IN COMPARISONS WITH THE PREVIOUS WORKS
V. CONCLUSIONS
ACKNOWLEDGMENT
REFERENCES

키워드

저자

• Thang Xuan Pham [ Dept. of Information and Communication Engineering Inha University ]
• Tuy Nguyen Tan [ Dept. of Information and Communication Engineering Inha University ]
• Phap Duong-Ngoc [ Dept. of Information and Communication Engineering Inha University ]
• Huyen Pham Thi [ Dept. of National Laboratory of Information Security Hanoi, Vietnam ]
• Hanho Lee [ Dept. of Information and Communication Engineering Inha University ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  한국차세대컴퓨팅학회 학술대회

• 간기

  반년간

• 수록기간

  2021~2025

• 십진분류

  KDC 566 DDC 004