Earticle

초록

영어

Low Density Parity Check codes are FEC codes and consequently data rate is more. They are linear error correcting codes for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance, Low Decoding Complexity. The main advantage of the parity check matrix is the decoder can correct all single-bit errors. In this Paper LDPC encoder and decoder architecture for coding 3-bit message vector will be analyzed and also designed using VHDL.

목차

Abstract
 1. Introduction
 2. System Design
  2.1. LDPC Algorithm
  2.2. Design of LDPC Architecture using VHDL Coding
 3. Encoder Design
 4. Channel Design
 5. Decoder Design
  5.1. Simulation Results
  5.2. Applications of LDPC
 6. Conclusion
 References

키워드

저자

• Gade Sribala [ Department of Electronics and Communication Engineering, Vignan’s Nirula Institute of Technology and Science for Women, Palakaluru, Guntur, AP, India ]
• D.V.N. Sukanya [ Department of Electronics and Communication Engineering, Vignan’s Nirula Institute of Technology and Science for Women, Palakaluru, Guntur, AP, India ]
• K.Gouthami [ Department of Electronics and Communication Engineering, Vignan’s Nirula Institute of Technology and Science for Women, Palakaluru, Guntur, AP, India ]
• Tai-hoon Kim [ Department of Convergence Security, Sungshin Women's University, 249-1, Dongseon-dong 3-ga, Seoul, 136-742, Korea ] Corresponding Author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Security and Its Applications

• 간기

  격월간

• pISSN

  1738-9976

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605