Earticle

공정 기술이 발전하면서 프로세서의 전력 밀도가 높아지면서 프로세서의 많은 부분이 가동되지 않는 상태에 놓이는 검은 실리콘 문제가 대두되었다. STTRAM (Spin Torque Transfer Random Access Memory)은 기존 SRAM에 비해 우수한 누수 전력 효율성 및 읽기 에너지 소모량으로 인해 이러한 문제를 해결할 새로운 온칩 메모리 소자로 주목받고 있다. 본 논문에서는 STTRAM만을 데이터 저장 공간으로 사용한 (SRAM-STTRAM 혼용이 아닌) L1 데이터 캐쉬와 명령어 캐쉬 메모리를 제안하고 이를 에너지, 성능, 면적 측면에서 평가한다. STTRAM을 L1 데이터 캐쉬 및 명령어 캐쉬에 모두 사용한 경우, 기존 SRAM으로 구성된 캐쉬 메모리 대비 최대 58% 정도의 에너지 소모를 절감할 수 있다. 또한, 빠른 읽기 성능 덕분에 STTRAM을 L1 명령어 캐쉬 메모리에 적용할 경우 약 3%의 성능 증가 효과도 가져온다. 면적 측면에서는 약 80% 정도의 면적을 SRAM 기반 캐쉬 메모리 대비 절감 가능하다.

As process technology advances, the dark silicon problem, which means a large portion of the processor components remains in the idle or inactive state, has emerged due to increased power density in processors. STTRAM (Spin Torque Transfer Random Access Memory) is one of the promising memory device technologies in the dark silicon era, which enables much lower leakage power consumption and higher read energy efficiency compared to SRAM cells. In this paper, we propose STTRAM-only (i.e., not SRAM-STTRAM hybrid) L1 data and instruction cache architecture and evaluate them in terms of energy, performance and area. In the case where STTRAM cells are used for both L1 data and instruction cache, energy consumption in the L1 caches is reduced by up to 58%. In addition, thanks to faster read access latency, we can improve performance by 3% when STTRAM cells are used for constructing the L1 instruction cache. In terms of area, using STTRAM cells reduces L1 cache area by up to 80% compared to using the conventional SRAM cells in the L1 caches.

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

As a powerful and flexible processor, the Graphic Processing Unit (GPU) can offer a great faculty in solving many high-performance computing applications. Sweep3D, which simulates a single group time-independent discrete ordinates (Sn) neutron transport deterministically on 3D Cartesian geometry space, represents the key part of a real ASCI application. The wavefront process for parallel computation in Sweep3D limits the concurrent threads on the GPU. In this paper, we present multi-dimensional optimization methods for Sweep3D, which can be efficiently implemented on the finegrained parallel architecture of the GPU. Our results show that the overall performance of Sweep3D on the CPU-GPU hybrid platform can be improved up to 4.38 times as compared to the CPU-based implementation.

This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays ("mesh", for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size $m{\times}m$ with static row/column buses to simulate the mesh of the larger size $n{\times}n$ with reconfigurable row/column buses ($m{\leq}n$). This means that if a problem can be solved in O(T) time by the mesh of size $n{\times}n$ with reconfigurable buses, then the same problem can be solved in O(Tn/m (n/m + log m)) time on the mesh of a smaller size $m{\times}m$ without a reconfigurable function. This time-cost is optimal when the relation $n{\geq}m$ log m holds (e.g., m = $n^{1-\varepsilon}$ for $\varepsilon$ > 0).

Vehicle detector system based on image processing technology is a significant domain of ITS (Intelligent Transportation System) applications due to its advantages such as low installation cost and it does not obstruct traffic during the installation of vehicle detection systems on the road[1]. In this paper, we propose architecture for vehicle detection by using image processing. The architecture consists of two main parts such as an image processing part, using high speed FPGA, decision and calculation part using CPU. The CPU part takes care of total system control and synthetic decision of vehicle detection. The FPGA part assumes charge of input and output image using video encoder and decoder, image classification and image memory control.

This paper presents processing-node status-based message scattering and gathering algorithms for multi-processor systems on chip to reduce the communication time between processors. In the message-scattering part of the message-passing interface (MPI) scatter function, data transmissions are ordered according to the proposed linear algorithm, based on the processor status. The MPI hardware unit in the root processing node checks whether each processing node's status is 'free' or 'busy' when an MPI scatter message is received. Then, it first transfers the data to a 'free' processing node, thereby reducing the scattering completion time. In the message-gathering part of the MPI gather function, the data transmissions are ordered according to the proposed linear algorithm, and the gathering is performed. The root node receives data from the processing node that wants to transfer first, and reduces the completion time during the gathering. The experimental results show that the performance of the proposed algorithm increases at a greater rate as the number of processing nodes increases.

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

In this paper we propose a method for verifying video in a video telephony system implemented in DM6446 DaVinci Processor. Each frame is categorized either error free frame or error frame depending on the predefined criteria. Human face is chosen as a basic means for authenticating the video frame. Skin color based algorithm is implemented for detecting the face in the video frame. The video frame is classified as error free frame if there is single face object with clear view of facial features (eyes, nose, mouth etc.) and the background of the image frame is not different then the predefined background, otherwise it will be classified as error frame. We also implemented the image histogram based NCC (Normalized Cross Correlation) comparison for video verification to speed up the system. The experimental result shows that the system is able to classify frames with 90.83% of accuracy.

운영 체제의 코어에 Intel PT가 포함된 경우, 크래시 발생 시 디버거는 프로그램 상태를 검사할 수 있을 뿐만 아니라 크래 시를 발생시킨 제어 플로우를 재구성할 수 있다. 또한, 커널 패닉 및 기타 시스템 정지와 같은 상황을 디버그하기 위해 실행 트레이스 범위를 전체 시스템으로 확장할 수도 있다. 2세대 PT인 WinIPT 라이브러리는 Windows 10 (버전 1809/Redstone 5) 에서 제공하는 IOCTL 및 레지스트리 메커니즘을 통해 프로세스 별 및 코어 별 트레이스를 실행할 수 있는 추가 코드가 포함 된 Intel PT 드라이버를 포함하고 있다. 즉 기존 1세대 PT에서 비정규화된 방식으로만 제한적인 접근이 가능했던 PT 트레이 스 정보를 2세대 PT에서는 운영 체제에서 제공하는 IOCTL 및 레지스트리 메커니즘을 통해 프로세스 별 및 코어 별 트레이 스를 실행할 수 있게 되었다. 본 논문에서는 1/2세대 PT를 이용하여 윈도우 환경에서 PT 데이터 패킷의 수집·저장·디코딩 및 악성코드 검출을 위한 방법을 비교·설명하였다.

If the operating system's core file contains an Intel PT, the debugger can not only check the program state at the time of the crash, but can also reconfigure the control flow that caused the crash. We can also extend the execution trace scop e to the entire system to debug kernel panics and other system hangs. The second-generation PT, the WinIPT library, inc ludes an Intel PT driver with additional code to run process and core-specific traces through the IOCTL and registry mec hanisms provided by Windows 10 (RS5). In other words, the PT trace information, which was limited access only by the first generation PT, can be executed by process and core by the IOCTL and registry mechanism provided by the operatin g system in the second generation PT. In this paper, we compare and describe methods for collecting, storing, decoding an d detecting malicious codes of data packets in a window environment using 1/2 generation PT.

This paper proposes a binarized neural network (BNN) processor supporting residual networks. The processor was fabricated in UMC 40-nm CMOS technology. Test results show that performance and energy efficiency are 1036.8 GOPS, and 66.5 GOPS/mW at 200MHz, respectively.

레이다 시스템의 경우, 타겟의 거리와 속도를 추출하기 위해 FFT (fast Fourier transform) 연산이 필수적으로 요구되며, 실시간 구현을 위해 고속으로 동작하는 FFT 프로세서의 설계가 필요하다. 고속 FFT 프로세서를 위한 하드웨어 구조로 완전 셔플 네트워크 (perfect shuffle network) 구조가 적합하며, 특히 초고속 연산을 위해 radix-4 기반의 이중 완전 셔플 네트워크 (twice perfect shuffle network) 구조가 가장 적절하고 볼 수 있다. 더불어, 다양한 속도 해상도를 요구하는 레이다 응용을 고려할 때, FFT 프로세서는 가변길이 FFT 연산을 지원할 필요가 있다. 이에 본 논문에서는 8~1024 포인트의 가변 길이 연산을 지원하는 이중 완전 셔플 네트워크 기반의 FFT 알고리즘을 제안하였으며, 이의 하드웨어 구조 설계 및 구현 결과를 제시한다. 제안된 FFT 프로세서는 HDL (hardware description language)을 활용하여 RTL (register transfer level) 설계가 수행되었으며, $0.65{\mu}m$ CMOS 공정을 활용하여 논리 합성한 결과, 총 3,293K개의 논리 게이트로 구현 가능함을 확인 할 수 있었다.

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

정보통신기술(ICT) 고도화에 따라 PDF, MS Office, HWP 파일로 대표되는 전자 문서형 파일의 활용이 많아졌고, 공격자들은 이 상황을 놓치지 않고 문서형 악성코드를 이메일과 메신저를 통해 전달하여 감염시키는 피해사례가 많아졌다. 이러한 피해를 막고자 AI를 사용한 악성코드 탐지 연구가 진행되고 있으나, PDF나 MS-Office와 같이 전 세계적으로 활용성이 높은 전자 문서형 파일에 비해 주로 국내에서만 활용되는 HWP(한글 워드 프로세서) 문서 파일은 양질의 정상 또는 악성 데이터가 부족하여 지속되는 공격에 강건한 모델 생성에 한계점이 존재한다. 이러한 한계점을 해결하기 위해 기존 수집된 데이터를 변형하여 학습 데이터 규모를 늘리는 데이터 증강 방식이 제안 되었으나, 증강된 데이터의 유용성을 평가하지 않아 불확실한 데이터를 모델 학습에 활용할 가능성이 있다. 본 논문에서는 HWP 악성코드 탐지에 있어 데이터의 유용성을 정량화하고 이에 기반하여 학습에 유용한 증강 데이터만을 활용하여 기존보다 우수한 성능의 AI 모델을 학습하는 준지도학습 기법을 제안한다.

With the advancement of information and communication technology (ICT), the use of electronic document types such as PDF, MS Office, and HWP files has increased. Such trend has led the cyber attackers increasingly try to spread malicious documents through e-mails and messengers. To counter such attacks, AI-based methodologies have been actively employed in order to detect malicious document files. The main challenge in detecting malicious HWP(Hangul Word Processor) files is the lack of quality dataset due to its usage is limited in Korea, compared to PDF and MS-Office files that are highly being utilized worldwide. To address this limitation, data augmentation have been proposed to diversify training data by transforming existing dataset, but as the usefulness of the augmented data is not evaluated, augmented data could end up harming model's performance. In this paper, we propose an effective semi-supervised learning technique in detecting malicious HWP document files, which improves overall AI model performance via quantifying the utility of augmented data and filtering out useless training data.

최근 IoT 산업에서 보안의 중요성이 증가하고 있으며, IoT (internet of things) 통신 산업에서는 소형의 하드웨어 칩이 필요하다. 이를 위해 본 논문에서는 대표적인 블록 암호 알고리즘인 AES (advanced encryption standard), ARIA (academy, research, institute, agency)와 CLEFIA를 통합한 저면적 암호화 프로세서를 제안한다. 제안하는 암호화 프로세서는 128 비트 기반으로 라운드 키 생성 과정과 암호화 및 복호화 과정을 하나로 공유하였으며, 각각 알고리즘의 구조를 공유 시켜 면적을 축소하였다. 더불어, 경량 IoT 기기를 포함한 대부분의 IoT 기기나 시스템에 적용이 가능하도록 구현하였다. 본 프로세서는 Verilog HDL (hardware description language)로 기술되었고65nm CMOS 공정을 통해 논리 합성하여 11,080개의 논리 게이트로 구현 가능함을 확인하였다. 결과적으로 각 알고리즘 개별 구현 대비 gate 수 총계에서 약42%의 이점을 보인다.

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

This paper presents an NC code post-processor that adjusts feedrates to keep the variation of metal removal rate along the tool paths minimum. Metal removal rate is estimated by virtually machining the part, whose surface model is built from a series of NC codes defined in operation plan, with cutting-tool-assembly models, whose geometry are defined in a machining database. The NC code post-processor modifies the feedrates by the adjustment rules, which are based on the machining knowledge for effective machining. This paper illustrates a procedure fur grouping machining conditions and we also show how to determine an adjustment rule for a machining-condition group. An example part was machined and it shows that the variation of cutting force was dramatically reduced after applying the NC code post-processor. The NC code post-processor is expected to increase productivity while maintaining the quality of the machined part.

보안 시스템에는 다양한 센서가 사용되고 있지만, 사생활 문제가 논란이 됨에 따라 레이다 센서가 대안으로 제시되고 있다. 그 중 PD (Pulse Doppler) 레이다는 짧은 펄스를 사용함으로써 수신부 복잡도가 증가하는 문제가 존재하나, FMCW (Frequency modulated continuous wave) 레이다는 그러한 제한이 적다는 장점이 있다. 그러나, FMCW 레이다는 2D-FFT (2-dimensional fast Fourier transform)를 사용하므로 기존의 센서에 비해서 상대적으로 높은 복잡도를 가지며, 정지해있는 표적에 대해 사람과 사물을 구분하기 어려운 단점이 있다. 따라서 본 논문에서는 1D-FFT와 위상 변화만으로 호흡 여부를 확인하여 사람과 사물을 구분할 수 있는 레이다 신호처리 프로세서의 설계 및 구현 결과를 제시한다. 제안된 신호처리 프로세서는 Verilog-HDL을 기반으로 설계하여 FPGA 디바이스에 기반하여 구현 및 검증하였다. LUT (Look up table) 6,425개, register 4,243개, 12,288개의 memory bit로 구현하여 92.1%의 정확도로 대상의 호흡 여부를 확인할 수 있음을 확인하였다.

Even though various types of sensors are being used for security applications, radar sensors are being suggested as an alternative due to the privacy issues. Among those radar sensors, PD radar has high-complexity receiver, but, FMCW radar requires fewer resources. However, FMCW has disadvantage from the use of 2D-FFT which increases the complexity, and it is difficult to distinguish people from objects those are stationary. In this paper, we present the design and the implementation results of the radar signal processor (RSP) that can distinguish between people and object by respiration measurement using phase estimation without 2D-FFT. The proposed RSP is designed with Verilog-HDL and is implemented on FPGA device. It was confirmed that the proposed RSP includes 6,425 LUT, 4,243 register, and 12,288 memory bits with 92.1% accuracy for target's breathing status.

레이다 시스템은 송신 파형에 따라 크게 PD (pulse Doppler) 레이다와 FMCW (frequency modulated continuous wave) 레이다로 구분되며, 송수신 특성에 따라 PD 레이다는 장거리 표적 검출에 유리한 반면, FMCW 레이다는 단거리 표적 검출에 적합한 특성을 갖는다. 이에 본 논문에서는 중/장거리 뿐 아니라 단거리 무인기 탐지를 위해 PD 레이다 시스템과 FMCW 레이다 시스템을 모두 지원 가능한 멀티모드 레이다 신호처리 프로세서 (RSP; radar signal processor)를 제안한다. 제안된 레이다 신호처리 프로세서는 Verilog-HDL을 이용하여 RTL 설계 후, Altera Cyclone-IV FPGA를 이용하여 구현 및 검증 되었다. 구현 결과, 총 19,623개의 logic elements, 9,759개의register, 그리고 25,190,400의 memory bit로 구현 가능함을 확인하였으며, 기존의 PD 레이다와 FMCW 레이다 신호처리 프로세서를 개별 구현한 경우에 비해 logic elements와 register 요구량이 약 43%와 39% 감소됨을 확인하였다.

Radar systems are divided into the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar depending on the transmission waveform. In particular, the PD radar is advantageous for long-range target detection, and the FMCW radar is suitable for short-range target detection. In this paper, we present design and implementation results for a multi-mode radar signal processor (RSP) that can support both PD and FMCW radar systems to detect unmanned aerial vehicles (UAVs) at short distances as well as long distances. The proposed radar signal processor can be implemented based on Altera Cyclone-IV FPGA with 19,623 logic elements, 9,759 registers, and 25,190,400 memory bits. The logic elements and registers of the proposed radar signal processor are reduced by approximately 43% and 30%, respectively, compared to the sum of logic elements and registers of the conventional PD radar and FMCW radar signal processor.

현재, 특정한 응용분야에 적합하도록 설계된 임베디드 시스템이 가전제품, 스마트폰, 자율주행 자동차, 로봇, 공장제어 등의 분야에 광범위하게 쓰이고 있다. 아울러, 임베디드 시스템을 구성하는 임베디드 프로세서의 성능에 지대한 영향을 미치는 DRAM의 중요성이 날로 증가되어, DRAM에 대한 연구가 산업계와 학계에서 활발하게 진행되고 있다. 모의실험을 통하여 임베디드 프로세서의 성능을 평가할 때 신뢰할만한 결과를 얻기 위하여, 보다 정확한 DRAM 모델을 갖추는 것이 중요하다. 본 논문에서는 이것을 위하여, DRAM 시뮬레이터와 연동할 수 있는 임베디드 프로세서 모의실험기를 개발하였다. 그리고, MiBench 임베디드 벤치마크를 입력으로, 싸이클 단위로 정확하게 동작하는 DRAM 모델이 임베디드 프로세서의 성능에 끼치는 영향을 분석하였다.

Currently, embedded systems designed for specific applications are used extensively in consumer electronics, smart phones, autonomous vehicles, robots, and plant control, etc. In addition, the importance of DRAM, which has a great influence on the performance of an embedded processor constituting an embedded system, has been increasing day by day, and research on DRAM has been actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of an embedded processor through simulation. In this paper, we developed an embedded processor simulator capable of interworking with a DRAM simulator. We also analyzed the influence of the DRAM model, which operates correctly on a cycle-by-cycle basis, on the performance of the embedded processor by using the MiBench embedded benchmark.

드론 또는 무인기의 정밀 자세제어를 위해서는 정확한 고도계가 필수적이며, 지상으로부터의 고도측정 정확도로 인해 레이다 고도계가 일반적으로 사용된다. 크기, 무게 및 전력소모 등에 제한으로 인해, 드론에 장착 가능한 레이다 고도계는 PD (pulse Doppler) 방식에 비해 낮은 복잡도를 갖는 FMCW (frequency modulated continuous wave) 방식이 적절하며, 특히, 짧은 송신시간으로 인해 드론 자체 움직임 (ego-motion)에 대응 가능한 fast-ramp FMCW 레이다가 보편적으로 활용된다. 이에, 본 논문에서는 fast-ramp FMCW 레이다 시스템을 위한 드론 고도 측정용 레이다 신호처리 프로세서 (RSP; radar signal processor)의 설계 및 구현 결과를 제시한다. 설계된 RSP는 Verilog-HDL을 이용하여 RTL 설계 후, Altera Cyclone-IV FPGA device를 활용하여 구현 및 검증되었다. 구현 결과, 총 27,523의 logic elements, 15,798개의 register, 138 Kbits의 memory로 구현 가능하며, 50MHz의 동작주파수로 100Hz의 실시간 고도측정이 가능함이 확인되었다.

Accurate altimetry is required for the reliable flight control of drones or unmanned air vehicles (UAVs), and the radar altimeter is commonly used owing to its accuracy for the ground level. Due to the limitation for size, weight and power consumption, the frequency modulated continuous wave (FMCW) radar is appropriate for drone because it has lower complexity than that of pulse Doppler (PD) radar. Especially, fast-ramp FMCW radar, which transmits linear FM signal during very short period, is generally utilized, because it is robust for the ego-motion of drone. Therefore, we present the design and implementation results of the radar signal processor (RSP) for fast-ramp FMCW radar system. The proposed RSP was designed with Verilog-HDL and implemented with Altera Cyclone-IV FPGA device. Implementation results show that the proposed RSP includes 27,523 logic elements, 15,798 registers and memory of 138Kbits and can measure the altimeter at the rate of 100Hz with the operating frequency of 50MHz.