Earticle

Purpose: The study aimed to examine the efficacy of the I.V. House UltraDressing for protecting peripheral intravenous catheters (PIVCs) in pediatric patients. Methods: This randomized controlled trial comprised 60 pediatric patients (aged 2e24 months): 30 in the experimental group and 30 in the control group. The PIVC dwell time and phlebitis scores were also reported for both groups. The degree of phlebitis was determined using the Visual Infusion Phlebitis Scale (VIPS) and was recorded every 8 hours from the start of antibiotic therapy until catheter removal. Results: The mean catheter dwell time in the experimental group (2.10 ± 1.55 days) was significantly longer than that in the control group (1.27 ± 0.45 days) (p < .01). However, there were no significant differences between the scores and signs of phlebitis in both groups (p > .05). Conclusion: The I.V. House UltraDressing is a useful device that can be used to increase catheter dwell time and protect and stabilize PIVCs in pediatric patients.

To increase the convenience in daily life activities, the Internet of Things (IoT) technology has been developed and used; it can achieve a hyper-connected society by connecting various devices and systems through the Internet. In building an IoT environment, the moving target defense (MTD) strategy is used as a method to construct an active defense strategy for a mission-critical system. However, there is a lack of indicators that can easily identify the various properties of the MTD strategy and enable in constructing and establishing a new MTD strategy-based protection plan. To solve this problem, in this paper, we survey various MTD strategy research results and analyze the research that has been conducted to derive the various properties of the three perspectives in the MTD strategy (When to move, What to move, How to move). In addition, based on the various derived properties, we propose a graph that can easily identify the various research results that appear. Additionally, it shows that the combination of various properties can be used as an indicator to understand the research direction of a new protection strategy research based on the software-defined MTD strategy for IoT device protection.

PPS 소자가 삽입된 N형 실리콘 제어 정류기(NSCR_PPS) 소자에서 채널차단영역의 이온주입 변화가 정전기 보호 성능에 미치는 영향을 연구하였다. 종래의 NSCR 표준소자는 on 저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 마이크로칩의 정전기보호소자로 적용이 어려웠다. 그러나 본 연구에서 제안하는 채널 차단 영역의 이온주입 조건을 변화시켜 각각 변형설계된 소자에서는 채널 차단 이온주입이 정전기 보호성능의 향상에 영향을 주는 중요한 파라미터였으며, CPS_PDr+HNF 구조의 변형소자 는 정전기보호소자의 설계창을 만족시키는 향상된 정전기보호성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different implant of channel blocking region was discussed for high voltage I/O applications. A conventional NSCR standard device shows low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified channel blocking structure demonstrate the improved ESD protection performance as a function of channel implant variation. Therefore, the channel blocking implant was a important parameter. Since the modified device with CPS_PDr+HNF structure satisfied the design window, we confirmed the applicable possibility as a ESD protection device for high voltage operating microchips.

본 논문에서는 고전압에서 동작하는 DDIC(display driver IC) 칩의 정전기 보호소자로 사용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘이 분석되었다. 이온주입 조건을 달리하는 매트릭스 조합에 의한 수차례의 2차원 시뮬레이션 및 TLP 특성 데이타를 비교한 결과, BJT 트리거링 후에 더블 스냅백 현상이 나타났으나 웰(well) 및 드리프트(drift) 이온주입 조건을 적절히 조절 함으로써 안정적인 ESD 보호성능을 얻을 수 있었다. 즉, 최적의 백그라운드 캐리어 밀도를 얻는 것이 고전압 동작용 정전기보호소 자의 고전류 특성에 매우 중요한 영향을 주는 임계인자(critical factor)임을 알 수 있었다.

In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

종래의 이중 확산된 드레인을 갖는 n형 MOSFET(DDD_NMOS) 소자는 매우 낮은 스냅백 홀딩 전압을 갖는 SCR 특성을 나타내므 로 정상적인 동작 동안 래치업 문제를 초래한다. 그러나, 본 연구에서 제안하는 counter pocket source (CPS) 구조를 갖도록 변형된 DDD_NMOS 구조의 SCR 소자는 종래의DDD_NSCR_Std 표준소자에 비해 스냅백 홀딩 전압과 온-저항을 증가시켜 우수한 정전기 보호 성능과 높은 래치업 면역 특성을 얻을 수 있는 것으로 확인되었다.

ABSTRACT A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

본 논문에서는 고전압에서 동작하는 마이크로칩의 안정하고 튼튼한 정전기 보호 성능을 구현하기 위해 이중 극성 소오스를 갖는 DPS_EDNMOS 변형소자가 제안되었다. 제안된 DPS는 N+ 소오스로 부터 전자 풍부 영역이 측면 확산되는 것을 방지하기 위해 N+ 소오스 측에 P+ 확산층을 의도적으로 삽입한 구조이다. 시뮬레이션 결과에 의하면 삽입된 P+ 확산층은 고전자 주입에 의해 발생 하는 깊은 전자채널의 형성을 효과적으로 막아주고 있음을 알 수 있었다. 따라서 종래의 EDNMOS 표준소자에서 문제시 되었던 더블 스냅백 현상을 해결할 수 있었다.

In this paper, modified EDNMOS device with DPS (double polarity source) structure are suggested to realize stable and robust ESD (electrostatic discharge) protection performance of high voltage operating microchip. This DPS structure inserts the P+ diffusion layer on N+ source side, which in intended to block lateral extension of the electron rich region from N+ source side. Based on our simulation results, the inserted P+ diffusion layer effectively prevents the formation of deep electron channeling induced by high electron injection. As a result, our proposed DPS_EDNMOS devices could overcome the double snapback effect of conventional Std_EDNMOS device.

본 논문에서는 ESD 방지를 위한 최적 방법론에 목표하여 확장된 드레인을 갖는 EDNMOS 소자의 더블 스냅백 현상 및 백그라운도핑 농도 (BDC)의 영향을 조사하였다. 고전류 영역에서 낮은 BDC를 가진 EDNMOS 소자는 강한 스냅백으로 인해 취약한 ESD 성능과 높은 래치업 위험을 가지게 되나, 높은 BDC를 가진 EDNMOS 소자는 스냅백을 효과적으로 방지할 수 있음을 알 수 있었다. 따라서 BDC 제어로 안정적인 ESD 방지 성능과 래치업 면역을 구현할 수 있음을 밝혔다.

High current behaviors of the extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOSFET) for electrostatic discharge (ESD) protection of high voltage operating LDI (LCD Driver IC) chip are analyzed. Both the transmission line pulse (TLP) data and the thermal incorporated 2-dimensional simulation analysis demonstrate a characteristic double snapback phenomenon after triggering of biploar junction transistor (BJT) operation. Also, background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the EDNMOS devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.

PPS 구조를 갖는 N형 실리콘 제어 정류기 소자에서 부분웰 구조가 정전기 보호 성능에 미치는 영향을 고찰하였다. 종래의 NSCR표준소자는 온-상태 저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 정전기 보호소자의 필요조건을 만족시키지못해 적용이 어려웠으나, 본 연구에서 제안하는 부분웰 구조를 갖도록 변형 설계된 NSCR-PPS 소자는 안정한 정전기보호 성능을나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

Electrostatic Discharge(ESD) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlledrectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. Aconventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapbackholding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However,our proposed NSCR_PPS devices with modified PPW demonstrate the stable ESD protection performance with high latch-upimmunity.

NESCR 구조의 정전기 보호소자가 고전압 동작용 I/O 응용을 위해 분석되었다. 기존의 NESCR 표준소자는 매우 낮은 스냅백 홀딩전압을 갖는 전형적인 SCR 특성을 나타내므로 정상적인 동작 동안 래치업 문제를 초래한다. 그러나 본 연구에서 제안하는 CPS및 부분적으로 형성된 P-well 구조를 갖는 NESCR_CPS_PPW 변형소자는 높은 온-저항과 스냅백 홀딩 전압을 나타내어 래치업면역 능력을 향상시킬 수 있었다.

An electrostatic discharge (ESD) protection device, so called, N-type embedded silicon controlled rectifier (NESCR), wasanalyzed for high voltage operating I/O applications. A conventional NESCR standard device shows typical SCR-likecharacteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, our modified NESCR_CPS_PPW device with proper junction/channel engineering such as counter pocket source(CPS) and partial P-well structure demonstrates highly latch-up immune current-voltage characteristics with high snapbackholding voltage and on-resistance.

기존의 NEDSCR 소자는 매우 낮은 스냅백 홀딩전압과 낮은 온-저항을 가져 정상적인 동작 동안 래치업을 초래하므로 ESD 보호소 자로 사용하는데 어려움이 있었다. 본 연구에서는 NEDSCR 소자의 시뮬레이션 및 TLP 테스트를 통해 이러한 단점들을 극복할 수 있는 새로운 방법을 제안하였다. 매우 우수한 ESD 보호 성능과 높은 래치업 면역 특성을 구현하기 위해 N+ 소오스 확산영역을 둘러싸는 P형의 CPS 이온주입공정을 추가함으로써 NEDSCR 소자의 스냅백 홀딩전압과 온 저항을 증가시켜 정전기 보호 성능을 개선시킬 수 있는 것으로 입증되었다.

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

PPS 소자가 삽입된 N형 실리콘 제어 정류기(NSCR_PPS)소자에서 게이트와 N+ 확산층 간격(Gate to Primary N+ diffusion Space;GPNS)의 변화가 정전기 보호 성능에 미치는 영향을 연구하였다. FPW 구조와 CPS 이온주입을 행하지 않은 구조를 갖는 종래의NSCR 표준소자는 on 저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 정전기 보호소자의 필요조건을 만족시키지못해 마이크로칩의 정전기보호소자로 적용이 어려웠다. 그러나 본 연구에서 제안하는 PPW 구조와 CPS 이온주입을 동시에 적용하여 변형설계된 소자에서는 GPNS의 변화가 정전기 보호성능의 향상에 영향을 주는 중요한 파라미터였으며, 정전기보호소자의 설계창을 만족시키는 향상된 정전기보호성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary N+ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

PPS 소자가 삽입된 부분웰 구조의 N형 실리콘 제어 정류기(NSCR_PPS) 소자에서 정전기 보호 성능의 향상을 위한 CPS 이온주입 조건의 최적화에 대해 연구하였다. 종래의 NSCR 표준소자는 on-저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 정전기 보호소자의 필요조건을 만족시키지 못해 적용이 어려웠으나, 본 연구에서 제안하는 CPS 이온주입과 부분웰 이온주입을 동시에 적용한 변형 설계된 소자의 경우 스냅백 홀딩 전압을 동작전압 이상으로 증가시킬 수 있는 향상된 정전기 보호성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

Objection of this research is to introduce a development model and a function to secure agents who working in field of protection to VIP, counterterrorism, disaster and safety control, and salvage requiring of brilliant security equipment to increase ability to deal with business. This research tried to give an explanation of purpose of this study by dividing development model into 4 areas. This device could monitor to confirm concentration, fatigue, mental change, checking life or death also could monitor location of agents through GPS system in real time. These lead finally for increasing business efficiency In this study, typical case sampling method was used. This is a method which can be claimed that same things can be shown in other cases if somethings were shown in some cases. Information for objects of study should be specifically provided in this method of study because this study is for specific location, objects, and cases so introduction to location and participant for study were needed. In this study, academic fields are divided as Security(Protection to VIP, Counterterrorism, Disaster and Safety Control, Salvage), Medicine(Otolaryngology, Neurosurgery, Neuropsychiatry, Ophthalmology) and Engineering(Information Technology, hardware production) and specialists who have over 10 year work experiences or doctoral and philosophy degree and specialists are chosen as fields and then we have sufficient information for study from each participant for 6 months. Finally, results of this study are conformed from participants to secure reliability and validity of results of this study. I would like to wish this product become popular and helpful to agents on site for security assurance and public order in the future.

태양광발전 설비의 고장 중 서지에 의한 고장이 전체 고장률의 20% 차지하고 있으며 발전 중 수십에서 수백 [A]의 에너지 방출과 인버터, 접속반 등의 전기적 손상은 전기안전사고로 이어지고 있다. 특히 낙뢰의 경우 전기회로에 이상 전압이 유기되어 절연을 파괴할 뿐만 아니라 이때 흐르는 전류는 화재의 원인이 되고 부품의 열화를 촉진하는 요인 으로 작용한다. 이러한 작용으로 도심 밖에서 주택, 아파트, 관공서 등의 도심 내부로 확산하고 있는 태양광 발전장치의 전기 안전 문제가 대두되고 있다. 낙뢰는 필드 기반 및 전도성 전기 간섭을 유발하기에 이 효과는 케이블 길이 또는 도체 루프 증가와 관련하여 증가한다. 또한 서지는 태양광 모듈, 인버터 및 모니터링장치뿐만 아니라 건물 설비의 장치도 손상하기에 최종적으로는 태양광발전시스템의 화재로 인한 운영 중단과 이에 따른 재정손실을 유발하게 시킬 수 있다. 따라서 본 논문에서는 태양광발전시스템의 낙뢰발생으로 인한 화재 및 전기안전사고 증가로 인하여 재산피해 및 인명피 해를 줄일 수 있는 목적으로 태양광발전장치의 낙뢰보호 시스템을 연구하고자 한다.

Among the failures of photovoltaic power generation facilities, failures caused by surges account for 20% of the total failure rate, and energy emissions of tens to hundreds [A] during power generation and electrical damage to inverters and connection boards lead to electrical safety accidents. In particular, in the case of lightning, an abnormal voltage is induced in an electric circuit to destroy insulation, and the current flowing at this time causes a fire and acts as a factor that accelerates the deterioration of parts. Due to this action, the problem of electrical safety of solar power generation devices spreading from outside the city center to the inside of the city center such as houses, apartments, and government offices is emerging. Since lightning strikes cause both field-based and conducted electrical interference, this effect increases with increasing cable length or conductor loops. In addition, surge damages not only solar modules, inverters and monitoring devices, but also building facilities, which can eventually cause operational shutdown due to fire of the photovoltaic power generation system and consequent financial loss. Therefore, in this paper, a lightning protection system for solar power generation devices is studied for the purpose of reducing property damage and human casualties due to the increase in fire and electrical safety accidents caused by lightning strikes in photovoltaic power generation systems.

Objective : The main concern during transfemoral carotid artery stenting (CAS) is preventing cerebral embolus dislodgement. We compared clinical outcomes and intraprocedural embolization rates of CAS using a distal filter protection device or proximal balloon occlusion device. Methods : From January 2011 to March 2015, a series of 58 patients with symptomatic or asymptomatic internal carotid artery stenosis ${\geq}70%$ were treated with CAS with embolic protection device in single center. All patients underwent post-CAS diffusion-weighted magnetic resonance imaging (DW-MRI) to detect new ischemic lesions. We compared clinical outcomes and postprocedural embolization rates. Results : CAS was performed in all 61 patients. Distal filter protection success rate was 96.6% (28/29), whose mean age was 70.9 years, and mean stenosis was 81%. Their preprocedural infarction rate was 39% (11/28). Subsequent DW-MRI revealed 96 new ischemic lesions in 71% (20/28) patients. In contrast, the proximal balloon occlusion device success rate was 93.8% (30/32), whose mean age was 68.8 years and mean stenosis was 86%. Preprocedure infarction rate was 47% (14/30). DW-MRI revealed 45 new ischemic lesions in 57% (17/30) patients. Compared with distal filter protection device, proximal balloon occlusion device resulted in fewer ischemic lesions per patient (p=0.028). In each group, type of stent during CAS had no significant effect on number of periprocedural embolisms. Only 2 neurologic events occurred in the successfully treated patients (one from each group). Conclusion : Transfemoral CAS with proximal balloon occlusion device achieves good results. Compared with distal filter protection, proximal balloon occlusion might be more effective in reducing cerebral embolism during CAS.

This paper deals with the two stage surge protection device by using varistor and LC low pass filter. Recently varistor alone has been used with overvoltage protection devices for the AC power mains and has same problems associated with high remnant voltage and noise. In this work, in order to improve the cutoff performance of surge protection device, the lightning surge protection device having two stage hybrid circuit for an AC single phase mains was designed and fabricated. Operation characteristics and surge clamping performance of the surge protection device in an $8/20{\mu}s$ surge current are investigated. As a consequence, it is found that the proposed two stage surge protective device for AC power mains has a variety of advantages such as a smaller clamping voltage, high frequency noise reduction and large clamping capacity.

Noise induced hearing loss (NIHS), the well-known occupational disease, is caused by continuous excessive noise. The prevention of NIHS is very important, because it is unrecoverable. There are some kinds of hearing protection device (HPD), and those are effective in preventing NIHS. But workers in noisy environment often resist to wearing them. Because they are ready - made products, so workers feel uncomfortable to wear. Also, they didn't maintain the conversation frequency range, so workers are hard to communicate in wearing them. To prevent hearing loss effectively, it is important that workers keep wearing HPD. Therefore, a HPD is needed to be comfortable to wear and be effective not only in hearing protection but also in preserving communication ability. So we proposed a custom - made hearing protection device in which a small acoustic filter is inserted. We designed several kinds of small acoustic filters and carried out some acoustic experiments for measuring characteristics of filters. We confirmed that acoustic transmission characteristic can be adjusted from experimental results using designed small acoustic filters. And we researched for the actual efficiency of a new developed custom - made hearing protection device using a small size acoustic filter. Also, we found out that workers are more satisfied with the new development than a former protection device from a workers' response.

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.