Earticle

본 논문에서는 Push-Push 구조와 고임피던스 인버터를 이용하여 개선된 VCO를 설계 및 제작하였다. 두 개의 고조파 발진기를 Push-Push 구조로 결합시킴으로써 기본주파수 억압특성을 개선하였으며, 고조파 출력을 향상시켰다. 이에 따른 위상잡음 증가는 고임피던스 인버터를 이용하여 공진기와 병렬선로 사이의 결합특성 개선을 통하여 억제하였다.

In this paper, improved VCO(voltage controlled oscillator) with push-push structure and high impedance-inverter is designed and implemented. Two harmonic oscillators are combined into push-push structure. As a result, the fundamental suppression and the output power have been progressed. For the improved coupling characteristics between hair-pin resonator and two parallel microstrip line using high impedance inverter, the phase noise has been suppressed.

RF 송수신기 설계 분야에서 활발하게 연구하고 있는 융복합 단일칩 설계 기술은 차내 무선망을 위한 차량 무선 단말기에도 적용 가능하며, 이의 실현을 통하여 좀 더 경제적이고 소형화된 차내 융복합 시스템을 구현할 수 있다. 제안된 광대역 전압제어 발진기는 차내 무선망에 사용할 수 있는 표준인 CDMA, PCS, GSM850, 끌림, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, DVB-H/DMB-T/H(L Band) 등의 주파수 대역을 만족시킬 수 있도록 제안된 frequency planning을 따른다. 또한, cross-coupled된 트랜지스터 한 쌍과 MOS varactor에 PMOS를 채택함과 동시에, capacitor array에서는 differential 스위칭을 사용함으로써 위상잡음을 개선하였다. 측정결과, 5.3~6.0 mW의 전력을 소모하며, 주파수 대역은 4.05~5.62 GHz (33%의 tuning range)이고 위상잡음은 1 MHz의 offset 주파수에서 -117.16 dBc/Hz이며 이때 figure of merit (FOM)은 180.5~180.8 이다.

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range (4.2~5.4 GHz) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is 5.3~6.0 mW at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is 180.84~180.5.

In this work, the review of phase noise in voltage controlled oscillator (VCO) which is very important system in all kinds of wireless communication system is presented. Such kinds of VCOs can be fabricated by hybrid method using PCB substrate or by semiconductor technology using silicon, GaAs, InP, complementary metal oxide semiconductor (CMOS), micro-electromechanical sytems (MEMS) and so on. Recently there are many kinds of design tools like ADS, AWAR etc. for RF system design. Especially, the phase noise is essential parameter to be considered during the design and simulation process. Optimization of such parameter is also important in simulation because phase noise cannot be totally eliminated but it can be reduced using different techniques. If phase noise is maximum in the signal, spectrum purity cannot be expected, eventually, the system will be failed to extract the real signal. That means, the performance of the overall system will not be degraded by improving the VCO phase noise performance

본 논문에서는 낮은 위상잡음 특성과 넓은 주파수 가변을 갖는 새로운 전압제어 발진기의 구조를 제안한다. 제한한 구조는 서셉턴스 기울기 파라미터를 높이기 위해 임피던스 변환기를 이용하여 직렬 공진 회로를 병렬 공진 회로로 변환하는 방법을 사용하고 있다. 제작한 전압제어발진기는 0V~9V 가변전압으로 10.1GHz~10.7GHz의 600MHz 주파수 가변과 -119dBc/Hz@1MHz 이하의 우수한 위상잡음 특성을 보인다. 측정된 고조파 억압특성은 28dB이상이다.

In this paper, a novel VCO (Voltage Controlled Oscillator) structure is proposed to achieve the characteristic of low phase noise and a wide frequency tuning range. The proposed scheme adopts an impedance transforming technique to change a series resonance into a parallel resonance for maximizing the susceptance slope parameter. The manufactured VCO shows a frequency tuning bandwidth of 600MHz from 10.1GHz to 10.7GHz with a tuning voltage varying from 0 to 9V, an excellent phase noise below -119dBc/Hz@1MHz offset. The harmonic suppression is measured above 28dB.

본 논문에서는 낮은 위상잡음과 고신뢰성을 갖는 전압제어 발진기를 비선형 설계하였으며 그 위상잡음을 Lesson식과 비교하여 잘 일치함을 확인하였다. 전압제어 발진기의 위상잡음을 개선하기 위하여 유전체 공진기와 결합하는 마이크로 스트립 라인을 고임피던스 변환기를 이용함으로써 공진회로의 Q값이 그대로 능동소자에 전달되도록 하였다. 또한 worst case 해석 및 part stress 해석을 수행함으로써 전압제어 발진기의 신뢰도를 높였다. 제작된 전압제어 발진기는 012 V의 제어전압에서 0.56 MHz/V의 튜닝대역을 가지고 있으며 160 mW의 DC 전력을 소모한다. 또한 -116.5 dBc/Hz @100KHz와 -96.51 dBc/Hz @10KHz의 우수한 위상잡음 특성과 7.33 dBm의 출력을 얻었다.

The VCO(Voltage Controlled Oscillator) with low phase noise and high reliability is implemented using nonlinear design, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise, and the qualify factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCO. The developed VCO has the oscillating tuning factor of 0.56MHz/V for the control voltage range of 012V This VCO requires the DC power of 160mW. The phase noise characteristics exhibit good performances of -96.51dBc/Hz @ 10KHz and -116.3dBc/Hz @ 100KHz, respectively. And, the output power of 7.33 dBm is measured.

본 논문에서는 도플러 레이더 시스템의 신호원이 되는 전압제어 발진기를 설계 및 제작하였다. 제안된 VCDRO는 CPW라인 형태를 이용하여 동조시키는 새로운 방법을 이용하였다. 유전체 공진기 기판 됫면에 바랙터 다이오드가 실장된 /2 길이를 갖는 CPW 회로를 구현하여 유전체공진기와 커플링을 시켰다. 바랙터 다이오드는 CPW 한쪽 끝에 실장을 하였다. 제안된 CPW 동조회로는 여러 개의 다이오드를 실장 할 수 있어 동조대역폭을 쉽게 늘일 수 있다. 동조된 전압제어 발진기는 바랙터 다이오드의 전압을 015V 로 가변시 12MHz 의 동조대역폭을 나타내었다. 제안된 CPW라인으로 동조된 위상고정 유전체 발진기는 10.5250Hz에서16.5dBm의 출력을 나타내었으며, 위상잡음은 -l15dBc/Hz@100kHz,-105dBcHz@10kHz,-102dBc/@1kHz 의 위상잡음 특성을 나타내었다.

In this paper, a VCDRO(Voltage Control Dielectirc Resonator Oscillator) for signal source of doppler radar system is designed and fabricated. The proposed VCDRO is made with new tuning mechanism using CPW line. The coplanar waveguide of /2 in length with varactor diode is placed on the metallization side under the dielectric resonator and coupled to it. Tuning varactor diode is mounted at one end of the CPW. The proposed circuit tuned by a CPW allows one more varactor diode to be mounted on the optimized CPW, where a greater sensitivity of frequency tuning is needed. With varying the biasing voltage for the varactor diode from 0 V to 15 V, output frequency tuning of 12 MHz is obtained. The PLDRO exhibits output power of 16.5 dBm with phase noise in the phase locked state characteristic of -115 dBc/Hz at 100 Hz, -105 dBc/Hz at the 10 kHz, and -102 dBc/Hz at 1 Hz offset from 10.525 GHz , respectively.

PLL(Phase-locked loop) is necessary in various field, for example, Radio communication system and Microprocessor. Also, it is important component to product receiver or transmitter. VCO(Voltage Controlled Oscillator) occurs sine wave or square wave which is depends on frequency controlled voltage. In addition, VCO is widely used frequency synthesize and clock restoration. It is the key of the PLL block diagram. This paper will explain VCO`s CMOS integrated circuit about mainly activate GHz band. APLL(Analog Phase-locked Loop) is in common use in VCO, but I will show the special VCO on DPLL(Digital Phase- locked Loop) which is more small than normal VCO. This paper consists of introduction, Ⅱ. The Structure of Ring-Oscillator VCO, Ⅲ. Simulation and Ⅳ. Conclusion.

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF-13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The value of MOSFET is calculated by using new drain current model.