Earticle

Recent embedded processors become to be multi-cored, due to the increased power consumption by higher operating frequencies. Multi-core processors stimulate applications to be parallelized. Since general purpose CPU has small number of core, which is optimized for serial processing, it has a limitation of parallel processing. To overcome this limitation, GPU is used for the parallel processing. In this paper, we implement GP-GPU of SIMT architecture for parallel processing in the embedded environment. The performance of the implemented GP-GPU is compared with the existing multi-core CPU of the embedded environment. The comparison results show the performance of parallel processing with the implemented GP-GPU is improved significantly.

This paper proposed a pedestrian recognition using CENTRIST algorithm on the basis of SIMT based Image signal processor. The conventional pedestrian recognition used algorithms such as Haar-like feature and HOG, but the huge amount of calculation makes it difficult to operate in real time in a restricted environment such as an embedded environment. This paper sought to improve the operation speed by processing the pedestrian recognition in parallel with the use of SIMT based Image signal processor and CENTRIST algorithm with less amount of calculation compared to other algorithms. The pedestrian recognition implemented in ISP exhibited the improved performance, which is about 2.7 times higher than that of the pedestrian recognition executed by Cortex-A9.

In this paper, we propose the optimized binarization in the GP-GPU. Because the binarinztion is esily paralledlized, we propose two ways of binary operations that utilize GP-GPU. The first method was to divide data load, subtraction and conversion, data store. The second method was processed collectibely. The second method was 2.52 times faster than the first method. After synthesizing the GP-GPU to the FPGA, the GP-GPU on the binarization were compared with the binarization on the ODROID XU. The binarization on the GP-GPU was 1.89 times faster than the binarization on the ODROID XU.

This paper proposes a multi-thread architecture-based Image Signal Processor (ISP). As the required image quality is gradually increasing in today’s society and the image processing algorithms are becoming more diversified, the burden of calculations in the main processor such as CPU is growing bigger. To solve these problems, an ISP was designed in order to reduce the burden on the main processor by applying the multi-thread architecture and applying various image processing algorithms, allowing a high performance processing. The proposed ISP has a multi-bank cache memory that can perform the multi-thread data and instructions with a hit-save-FIFO and latency hiding unit. The proposed ISP was verified with Virtex-7 FPGA and showed about 2.4 times higher processing speed compared to the conventional DSP.

In this paper, a warp scheduler is proposed for the improvement of multi-core stream processor based GP-GPU performance. The proposed warp schedulers are divided into odd and even warps, which are issued separately by applying the dual-warp issue. Furthermore, it can simultaneously process up to four instructions because each warp can issue two instructions through superscalar issue. The superscalar issue has a limitation in that it cannot simultaneously process two instructions having data dependence. To solve this limitation, the warp scheduler determines the instruction issuance by testing the issuing condition of the multi-core processor and the read/write register dependence. For scheduling algorithm, the round-robin algorithm was used. To measure the performance of multi-core stream processors, the Gaussian filter mask processing result of the GP-GPU using the proposed warp scheduler was compared with that of the multi-core CPU on various embedded platforms. The experiment results showed that the processing speed of the GP-GPU using the warp scheduler was 6-7 times faster. The GP-GPU also performed better on an image processing application.

In this paper, a Parallel Multiprocessor (PM) based on SIMT (Single Instruction and Multiple Threads) architecture is proposed. With co-issue architecture and multi-dimensional parallelism implemented in high-effective PM, Embedded Graphics Processing Unit (EGPU) provides great performance for various situations, such as general purpose computing, 3D scene rendering, and graphics processing. Application programs are departed into separated threads. Allocated by Thread Processing Unit (TPU), separated threads can be executed in parallel. Parallelism in different hierarchy and dimension are implemented by Multi-Dimensional Parallelism Processor (MD-PP), which has made a proper trade-off between performance and cost. Additionally, PM improves the hardware occupancy with its co-issue architecture and internal bus accessing mechanism to meet the demand of processing capability. Its unified shading architecture also helps to hide processing latency. PM can execute 4 basic operations in the best case and 2 in the worst case within each clock cycle. With 32nm process technology and 200MHz clock frequency, PM’s area is about 5104494um2, power consumption is about 101.838mW, and it can process nearly 28M vertices or fragments in average. Experimental results show that the MD-PP based PM can process data with high performance and get a balance between efficiency and hardware consumption simultaneously.

본 논문에서는 디스플레이 장치의 화면을 픽셀 단위로 구성하는 Rasterizer의 가속화를 위하여 SIMT구조의 GPGPU(General Purpose computing on Graphics Processing Units)를 사용하였다. GPU는 많은 수의 ALU를 가지고 있고, 병렬처리하기 때문에 연산처리가 매우 빠르다. 따라서 본 논문에서는 연산을 순차적으로 수행하는 CPU와 연산을 병렬적으로 수행하는 GPU를 이용하여 3D그래픽스 모델을 생성하는 rasterizer를 구현했다. 한 프레임 생성 시 Intel CPU를 이용한 rasterizer보다 본 논문에서 제안하는 rasterizer가 1.45배 좋은 성능을 확인하였다.

In this paper, SIMT structure based GPGPU (General Purpose Computing on Graphics Processing Units) is used for accelerating the Rasterizer which constitutes the screen of the display device in pixel unit. The GPU has a large number of ALUs, and the processing is very fast because of parallel processing. Therefore, in this paper, we implemented a rasterizer that generates a 3D graphics model using a CPU that performs operations sequentially and a GPU that performs operations in parallel. We confirmed that proposed rasterizer in this paper is 1.45 times better than rasterizer using Intel CPU when generating one frame.

본 논문은 그래픽 처리 뿐 만 아니라 범용 연산의 가속화를 지원하기 위한 SIMT 구조 GP-GPU의 Dispatch Unit과 Operand Selection Unit을 제안한다. Warp Scheduler로부터 발행된 명령어에서 사용되는 Operand의 모든 정보를 Decoding 하면 불필요한 Operand Load가 발생하여 레지스터 부하가 발생 한다. 이러한 문제점을 해결하기 위해 Pre-decoding방법을 사용하여 Operand의 정보만을 먼저 Decoding 하여 Operand Load를 줄이고, 레지스터의 부하를 줄일 수 있는 방법을 제안한다. 제안하는 Dispatch Unit에서 나온 Operand 정보들을 레지스터 뱅크 충돌을 방지하는 방법을 적용한 Operand Selection Unit에 전달해 전체적인 처리 성능을 향상 시켰다. Modelsim 10.0b를 이용하여 Warp Scheduler로부터 발행된 10,000개의 임의의 명령어를 처리하여 소요되는 총 Clock Cycle을 측정하였다. 본 논문에서 제안한 Pre-Decoding 기능을 탑재한 Dispatch Unit과 Operand Selection Unit을 적용하여 기존의 방법들 보다 각각 약 11%, 24%의 처리 효율이 증가한 것을 확인 할 수 있었다.

This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.

본 논문은 SIMT 구조 기반의 멀티코어 GPGPU의 통합 ALU를 설계하였다. 조건부 분기 명령어, 데이터 이동 명령어, 정수형 산술 연산 명령어, 부동소수점 산술 연산 명령어를 처리할 수 있으며 멀티코어 GPGPU의 다양한 형태의 병렬처리 기능을 지원하기 위하여 다 수의 ALU가 탑재된다. 각 명령어 연산의 처리방식의 공통성을 회로 수준에서 통합하여 최소의 크기로 ALU를 설계하는 것이 본 논문의 주안점이다. 모든 명령어는 테스트 프로그램을 작성하여 실험하였고 CPU로 연산한 결과와 비교하여 본 논문의 ALU가 정상적으로 동작함을 검증하였다. 본 논문에서 설계한 통합 ALU의 크기는 약 2만 게이트이며 최대 동작주파수는 430MHz이다.

This paper describes an implementation of a unified ALU on multi-core GPGPU based on SIMT architecture. Our unified ALU can operate conditional branch instructions, data movement instructions, integer arithmetic instructions and floating-point arithmetic instructions. Since multi-core GPGPU contains a lot of ALU for parallel processing of various types, the main point of this paper is to design the minimum size ALU by unifying similar processing of each operations on circit level. All instrunctions were tested by making a test program. And we compare this results with results of CPU operations to verify our ALU. Our unified ALU's gate size is approximately 20,000 and the maximum operation frequency is 430MHz.

본 논문에서는 다양한 영상 전처리 알고리즘들을 적용할 수 있고, 영상 인식과 같이 ISP 응용 프로그램을 병렬로 처리 가능한 SIMT(Single Instruction Multiple Threads) 기반 Image Signal Processor를 제안하였다. 기존의 ISP는 입력 영상의 품질 개선을 위하여 영상 개선 알고리즘이 하드웨어로 설계되어 처리 속도는 빠르지만 다양한 영상 처리 알고리즘에 따라 성능 최적화에 어려움이 있었다. 제안한 ISP는 명령어를 기반으로 한 프로세서로서 다양한 영상 처리 알고리즘을 수행하고 SIMT 구조를 적용하여 알고리즘을 병렬로 수행해 성능을 개선하였다. 제안하는 ISP를 검증하기 위해 Xilinx Virtex-7을 탑재한 VC707 Board를 사용하였으며 cell multicore processor와 비교했을 경우 수행시간이 약 71%, ARM Cortex-A9과 ARM Cortex-A15와 비교하였을 경우 각각 63%, 33% 성능을 개선하였다.

In this paper, we proposed SIMT based Image Signal Processor which can apply various image preprocessing algorithms and allow parallel processing of application programs such as image recognition. Conventional ISP has the hard-wired image enhancement algorithm of which the processing speed is fast, but there was difficult to optimize performance depending on various image processing algorithms. The proposed ISP improved the processing time applying SIMT architecture and processed a variety of image processing algorithms as an instruction based processor. We used Xilinx Virtex-7 board and the processing time compared to cell multicore processor, ARM Cortex-A9, ARM Cortex-A15 was reduced by about 71 percent, 63 percent and 33 percent, respectively.

본 논문은 SIMT(Single Instruction Multi Thread)구조 GP-GPU(General Purpose Graphic Processing Unit)에서 그래픽 어플리케이션 성능을 향상시키기 위해 타일 기반 그래픽 파이프라인 구조를 제안한다. 타일 기반 그래픽 파이프라인 구조는 병렬적으로 Rasterization 단계를 처리하고, 불필요한 그래픽 처리 연산은 수행하지 않는다. SIMT구조를 통해 대용량 데이터를 병렬로 처리하여 연산 성능을 향상시켰고, 이는 3D 그래픽 파이프라인 처리의 성능을 향상하였다. 제안하는 구조를 통해 3D 그래픽 어플리케이션을 처리할 때 3D 모델을 구성하는 정점 데이터가 많아 질수록 높은 효율을 보인다. 제안하는 구조는 'RAMP'와 기존의 선행 연구를 비교하여 약 1.18배에서 최대 3배까지의 처리 성능 향상을 확인하였다.

This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.

본 논문은 Memory Latency Penalty를 개선한 SIMT Architecture 기반 Stream Processor의 Memory Operation System Architecture를 제안한다. 제안하는 구조는 Non-Blocking Cache Architecture를 적용하여 기존의 Blocking Cache Architecture에서 발생하는 Cache Miss Penalty를 개선하였고 다양한 알고리즘의 처리속도를 비교하여 제안하는 Memory Operation System Architecture를 적용한 Stream Processor의 성능 향상을 검증하였다. 실험은 각 알고리즘의 Memory 명령어의 비율에 따라 향상된 성능을 측정하여 Stream Processor의 성능이 최소 8.2%에서 최대 46.5%까지 향상됨을 확인하였다.

In this paper, we propose a memory operation system architecture for memory latency penalty reduction in SIMT architecture based stream processor. The proposed architecture applied non-blocking cache architecture to reduce cache miss penalty generated by blocking cache architecture. We verified that the proposed memory operation architecture improve the performance of the stream processor by comparing processing performances of various algorithms. We measured the performance improvement rate that was improved in accordance with the ratio of memory instruction in each algorithm. As a result, we confirmed that the performance of stream processor improves up to minimum 8.2% and maximum 46.5%.

본 논문은 SIMT구조의 GPGPU에서 적은 core수로 고성능을 달성하기 위한 구조를 제안하고 설계하였다. 모바일기기에 적용하기 위한 GPGPU는 소모전력대비 성능을 높이기 위한 구조가 필수적이다. 소모전력을 줄이기 위해서 core수가 줄어든 대신 성능을 높이기 위해 thread를 관리하기 위한 warp scheduler의 size를 4로 하여 일반적인 GPGPU의 32 보다 크게 줄였다. Warp size를 적게 되면 pipeline의 idle cycle수를 줄일 수 있고 cache 메모리 접근시 miss penalty를 줄이기 위한 memory latency 적용이 효율적이다. 설계된 GPGPU는 부동소수점 연산을 포함하는 테스트 프로그램으로 연산 성능을 측정하고 28nm CMOS공정으로 소비전력을 측정하여 전력당 성능지수로 104.5GFlops/Watt를 얻었다. 본 논문의 결과는 Nvidia의 Tegra K1과 비교하였을 때 약 4배 우수한 전력당 성능지수를 보였다.

This paper proposed and designed a structure to achieve high performance with a small number of cores in GPGPU with SIMT structure. GPGPU for application to mobile devices requires a structure to increase performance compared to power consumption. In order to reduce power consumption, the number of cores decreased, but to improve performance, the size of the warp scheduler for managing threads was set to 4, which was greatly reduced than 32 of general GPGPU. Reducing warp size can reduce the number of idle cycles in pipelines and efficiently apply memory latency to reduce miss penalty when accessing cache memory. The designed GPGPU measured computational performance using a test program that includes floating point operations and measured power consumption through a 28nm CMOS process to obtain 104.5GFlops/Watt as a performance per power. The results of this paper showed about four times better performance per power compared to Tegra K1 of Nvidia