Earticle

초록

영어

In this paper, we propose the optimized binarization in the GP-GPU. Because the binarinztion is esily paralledlized, we propose two ways of binary operations that utilize GP-GPU. The first method was to divide data load, subtraction and conversion, data store. The second method was processed collectibely. The second method was 2.52 times faster than the first method. After synthesizing the GP-GPU to the FPGA, the GP-GPU on the binarization were compared with the binarization on the ODROID XU. The binarization on the GP-GPU was 1.89 times faster than the binarization on the ODROID XU.

목차

Abstract
 1. Introduction
 2. Binarization
  2.1 YUV 4:2:0 planar format
  2.2 Binarization
 3. Binarization on GP-GPU
  3.1 Memory Structure of GP-GPU
  3.2 Parallelization of binarization using GP-GPU
 4. Design and Verification of GP-GPU
  4.1 Verification of Simulation Design
  4.2 FPGA Design Verification
 5. Conclusion
 References

키워드

저자

• Seong Hyeon Han [ Department of Computer Engineering, Seoekyeong University, Seoul, Korea ]
• Suk Won Yoo [ Department of Computer Science, Seokyeong University, Seoul, Korea ] Corresponding author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Culture Technology(IJACT)

• 간기

  계간

• pISSN

  2288-7202

• eISSN

  2288-7318

• 수록기간

  2013~2025

• 등재여부

  KCI 등재

• 십진분류

  KDC 600 DDC 700