Earticle

초록

영어

This paper proposes a multi-thread architecture-based Image Signal Processor (ISP). As the required image quality is gradually increasing in today’s society and the image processing algorithms are becoming more diversified, the burden of calculations in the main processor such as CPU is growing bigger. To solve these problems, an ISP was designed in order to reduce the burden on the main processor by applying the multi-thread architecture and applying various image processing algorithms, allowing a high performance processing. The proposed ISP has a multi-bank cache memory that can perform the multi-thread data and instructions with a hit-save-FIFO and latency hiding unit. The proposed ISP was verified with Virtex-7 FPGA and showed about 2.4 times higher processing speed compared to the conventional DSP.

목차

Abstract
 1. Introduction
 2. Image Processing
 3. Proposed ISP Architecture
  3.1. Multi-Thread Processor based Architecture
  3.2. Multi-banked Cache Memory
  3.3. Cache Miss Handling Architecture with Hit-Save-FIFO
  3.4. Memory Latency Hiding
 4. Implementation
 5. Conclusions
 Acknowledgments
 References

키워드

저자

• Yun-Seop Hwang [ Department of Computer Engineering, Seokyeong University, KOREA ]
• Jun-Mo Jeong [ Department of Electronic Engineering, Seokyeong University, KOREA ] Corresponding author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Software Engineering and Its Applications

• 간기

  월간

• pISSN

  1738-9984

• 수록기간

  2008~2016

• 등재여부

  SCOPUS

• 십진분류

  KDC 505 DDC 605