Earticle

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

Gyroscopes applications are widely used for measuring angular velocity and angular rotation of objects. For working of a vibratory gyroscope, it needs to be excited at its resonant frequency. An electronic circuit is necessary to drive gyro vibrating. This circuit is also named oscillation loop. To get best performance of a gyro, the oscillation loop has to drive gyro oscillating at its fixed resonant frequency and maintain gyro's vibration amplitude at prescribed value. That means the oscillation loop has two parts: phase (frequency) control part and amplitude control part. This paper is written to introduce phase locked loop (PLL) technique to design a phase control loop for vibratory gyroscopes, in this case is a hemispherical resonating gyroscope (HRG).

근 전자 정보 통신 기술의 발전으로 개개인이 요구하는 정보의 전송량도 증가하고 있다. 특히 CATV의 전송량 증가에 따른 전송 성능의 향상이 불가피하다. 따라서 본 논문에서는 DOCSIS(Data-Over-Cable Service Interface Specifications) 2.0 요구 규격을 만족하는 CATV 전송 시스템에서 Bit Error Rate(BER)에 따른 최적의 Signal to Noise Ratio(SNR) 성능 요구 특성을 얻기 위한 위상 잡음 특성을 분석하였다. 특히 개발된 시뮬레이터를 이용하여 CATV 전송 시스템 위상 잡음 특성 요구 규격을 만족하는 Phase Locked Loop(PLL) 구성 요소 파라미터 값들을 도출하였다. 제시된 방법은 향후 초고속 CATV 전송 시스템의 위상잡음 관련 성능 요구 규격 도출에 이용될 수 있다.

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.

본 연구에서는 초 광대역에서 적용 가능한 저위상 잡음 PLL의 구조개선, 회로 보완, 설계 및 구현 방법 개선 등을 통해 초 광대역에서 저위상 잡음 특성을 갖는 PLL을 분석하고 성능 요구 규격을 만족하는 PLL 구현에 대해 소개하였다. 먼저 에질런트사의 ADS(Advanced Designed System)를 이용한 시뮬레이션을 통해 초 광대역 시스템용 PLL의 파워 특성, 위상잡음, 하모닉 특성 등을 분석하였고 분석 결과를 요구 규격과 비교하였다. 이를 토대로 저위상 잡음을 갖는 PLL을 구현하였다. 성능 측정결과를 통해 제시한 요구 규격을 만족 시키는 PLL의 구현을 확인하였다. 본 PLL은 초 광대역을 사용하는 서비스의 트랜시버에 유용하게 쓰일 것이다.

In this paper, we have introduced a new way to design low phase noise PLL which can apply to the Ultra wideband as meeting performance requirements based on structure improvement, circuit supplement, upgraded design method. Before development of the PLL, we simulated spectrum power, phase noise, harmonic characteristic by using ADS(Advanced Designed System). And, we compared result between measurement and simulation. Finally, we confirm a satisfying result which meet performance requirements between required standard and measured value. It will be useful for transceiver of service which operate in Ultra wideband.

FMCW 레이더에서 주파수 램프 신호를 발생시키기 위하여 필요한 타입-3 PLL의 설계 가이드를 제시하였다. 그러기 위해서 개루프 전달함수의 크로스오버 주파수를 1 Hz로 정규화 한 조건에서 Pspice 시뮬레이션을 통하여 폐루프 특성을 비교하였다. 결론적으로 타입-3 PLL의 1) 위상여유는 45도로 하고, 2) 두 개의 영점은 같도록 하며, 3) PLL 차수를 높이기 위한 극점은 개루프 전달함수의 크로스오버 주파수보다 10배 정도 크게 할 것을 권한다.

A design guide to type-3 PLLs for FMCW radars is provided. To do that, the cross-over frequencies of the open-loop transfer functions were normalized to 1 Hz and closed-loop properties were compared through simulations using Pspice. As a result, several guides to design type-3 PLLs were provided: 1) secure 45 degrees of phase margin, 2) locate two zeroes at an identical frequency, and 3) poles may be added to raise order of the PLL at higher frequencies than the cross-over frequency of the open-loop transfer function about ten times.

본 논문은 레이더 시스템에 적용되는 고성능 PLL 주파수 합성기를 설계하고, 그 성능을 분석하였다. 소형화 제작을 위해 PLL 간접합성방식을 적용하였으며, 광대역특성에서 우수한 위상잡음과 고속의 주파수합성시간을 갖기 위해 offset 방식의 PLL에 DDS를 기준신호로 설계 하였다. 또한, offset PLL에서 고속의 주파수 변환을 위해 DAC를 이용하여 coarse tune을 적용하였다. 이러한 구조에서의 성능 예측을 위해 각각의 잡음원에 대해 모델링을 적용하여 출력위상잡음을 예측하였으며, 제작결과와 비교 분석하였다. 그 결과 simulation과 측정결과가 일치함을 확인하였으며, 100KHz 옵셋 주파수에서 -126dBc/Hz의 우수한 위상잡음 특성과 10usec 이내의 고속의 주파수변환시간을 갖는 항공기용 레이더 주파수합성기를 설계하였다.

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

This paper suggests a simple method to solve the clock skew problem generated on two or several separate chips when voltage difference, or gradient, occurs between/among the chips. Generation and distribution of clock signals with minimum skews becomes a critical factor in overall system performance in today’s GHz operation speed. With a few connection lines, similar to Data Bus, between two chips, named CBL (Clock Bus Line), a multi-chip synchronization method is newly proposed and proved through simulations and TTL chip measurements. With 2% of supplied voltage differences in different chips, within 3% of the period clock skew is guaranteed in this new scheme. A feasible way of implementation of this CBL method in today’s integrated circuits is also described along with CMOS layout.

Phase frequency detector is the main component that is used in almost all high speed communication system especially in sensors. With the improving technology it is important for phase frequency detector to meet the requirement of modern communication system. Such requirements can be improved delay and less power consumption. With this idea this paper presents the Phase Frequency Detector having less power consumption and minimal delay. Conventional latch based phase frequency detectors are most commonly used, therefore we propose an enhanced phase frequency detector which can meet the requirement of modern circuits and will reduce the shortcomings of conventional circuit. In this paper standard D flip flop is simulated and then a comparison is made between conventional and proposed model .The proposed model uses two extra transistors to reduce the blind zone, dead zone which ensures improved device characteristics. Simulations are done using tanner v14.11 tools with .35 μm CMOS technology.

This paper intends to design a high-efficient grid connected three-phase three-level T-type photovoltaic inverter system which is operated with conjunction with grid. Different from the two-level topology mainly used previous, switch elements are increased by 6 pieces, it has the advantages such as the efficiency of the inverter, less stress in the switching elements, and less harmonic component in the output current. This paper will suggest the boost convert always supplying constant DC voltage for a three-phase three-level T-type photovoltaic inverter, and also presents the stability and excellence of the 3 level boost converter through experiments. Also, it offers the stable and high-efficient MPPT algorism and through solar irradiation change experiment and MPPT efficiency assessment, the excellence and efficacy of three-level T-type inverter was verified from experiments.

본 논문은 캐리어 주파수가 240 GHz인 THz 대역 송수신기에 있어서, 서브하모닉 믹서의 LO 주파수로 사용되는 120 GHz 국부발진기의 설계 및 제작에 관한 것이다. 120 GHz 국부발진기는 40 GHz PLL(Phase Locked Loop), 40 GHz 대역통과필터(Band Pass Filter), 3 체배기(frequency tripler), 120 GHz 대역통과필터로 구성되어 있으며, 3 체배기는 상용품을 이용하였다. 40 GHz PLL의 위상잡음은 100 kHz offset 주파수에서 -105 dBc/Hz의 성능을 보였고, 120 GHz의 대역통과필터의 중심주파수 119 GHz, 대역폭 5 GHz 일 때 삽입손실은 1.3 dB로 측정되었다. 제작된 120 GHz 국부발진기의 최종 출력은 6.6 dBm이었다.

In this paper, a 120 GHz local oscillator(LO) for the sub-harmonic mixer in the THz transceiver with a carrier frequency of 240 GHz was designed and fabricated. A 120 GHz local oscillator was composed of 40 GHz PLL(Phase Locked Loop), 40 GHz BPF(Band Pass Filter), frequency tripler and 120 GHz BPF. The commercial model of the frequency tripler was used. The measured result of the 40 GHz PLL showed the phase noise of -105 dBc/Hz at the 100 kHz offset frequency. The measured result of 120 GHz BPF showed the insertion loss of 1.3 dB at center frequency of 119 GHz with bandwidth of 5 GHz. The output power of 120 GHz LO was measured to 6.6 dBm.

최근 전자 정보 통신 기술의 발전으로 개개인이 요구하는 정보의 전송량도 증가하고 있다. 특히 CATV의 전송량 증가에 따른 전송 성능의 향상이 불가피하다. 따라서 본 논문에서는 DOCSIS(Data-Over-Cable Service Interface Specifications) 2.0 요구 규격을 만족하는 CATV 전송 시스템에서 Bit Error Rate(BER)에 따른 최적의 Signal to Noise Ratio(SNR) 성능 요구 특성을 얻기 위한 위상 잡음 특성을 분석하였다. 특히 개발된 시뮬레이터를 이용하여 CATV 전송 시스템 위상 잡음 특성 요구 규격을 만족하는 Phase Locked Loop(PLL) 구성 요소 파라미터 값들을 도출하였다. 제시된 방법은 향후 초고속 CATV 전송 시스템의 위상잡음 관련 성능 요구 규격 도출에 이용될 수 있다.

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.