Earticle

초록

영어

This paper suggests a simple method to solve the clock skew problem generated on two or several separate chips when voltage difference, or gradient, occurs between/among the chips. Generation and distribution of clock signals with minimum skews becomes a critical factor in overall system performance in today’s GHz operation speed. With a few connection lines, similar to Data Bus, between two chips, named CBL (Clock Bus Line), a multi-chip synchronization method is newly proposed and proved through simulations and TTL chip measurements. With 2% of supplied voltage differences in different chips, within 3% of the period clock skew is guaranteed in this new scheme. A feasible way of implementation of this CBL method in today’s integrated circuits is also described along with CMOS layout.

목차

Abstract
 1. Introduction
 2. Clock Distribution technique with CMOS Ring Oscillator Network
  2.1. CMOS Ring Oscillator Network
  2.2. Clock Signals Generation and Synchronization Technique with Two Oscillator Networks
  2.3. Hardware Implementation and Test with Low-Speed TTL Chips
 3. Spice Simulations and Measurements
  3.1. With the Same Supply Voltage
  3.2. Proposed Clock Bus Line Synchronization Technique with voltage differences
 4. Conclusion
 References

키워드

저자

• Kang-In Heo [ Dept. of Electronic Engineering, Hallym University, Gangwon-do, KOREA ]
• Sung-Jin Kim [ Dept. of Electronic Engineering, Hallym University, Gangwon-do, KOREA ]
• Hyun-Su Kim [ Dept. of Electronic Engineering, Hallym University, Gangwon-do, KOREA ]
• Gyu Moon [ Research Institute of Informatic and Electronic Engineering, Gangwon-do, KOREA ] Corresponding Author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605