Earticle

초록

영어

Phase frequency detector is the main component that is used in almost all high speed communication system especially in sensors. With the improving technology it is important for phase frequency detector to meet the requirement of modern communication system. Such requirements can be improved delay and less power consumption. With this idea this paper presents the Phase Frequency Detector having less power consumption and minimal delay. Conventional latch based phase frequency detectors are most commonly used, therefore we propose an enhanced phase frequency detector which can meet the requirement of modern circuits and will reduce the shortcomings of conventional circuit. In this paper standard D flip flop is simulated and then a comparison is made between conventional and proposed model .The proposed model uses two extra transistors to reduce the blind zone, dead zone which ensures improved device characteristics. Simulations are done using tanner v14.11 tools with .35 μm CMOS technology.

목차

Abstract
 1. Introduction
 2. Conventional PFD
 3. Enhanced PFD
 4. Simulations and Results
 5. Conclusion
 References

키워드

저자

• Latika Gulihar [ M.Tech scholor, YMCAUST ] Corresponding author
• Bal Krishan [ AP, YMCAUST ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Signal Processing, Image Processing and Pattern Recognition

• 간기

  격월간

• pISSN

  2005-4254

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605