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스마트폰과 같은 이동형 장치들은 계산 성능이나 메모리 크기, 배터리 전력량 등의 한계로 인해 엔터테인먼트 애플리케이션이 요구하는 상호작용성을 보장하기 어렵다. 이를 해결하기 위해 본 논문에서는 상호작용이 필수적인 애플리케이션의 응답 속도를 개선할 수 있는 코드 수준 병렬화 방법론을 제안한다. 이 방법을 적용하면, 스마트폰 등에서 제공하는 멀티코어 아키텍쳐를 바탕으로 기존 애플리케이션의 모노코어 알고리즘을 복잡한 재설계 없이 코드 수준에서 병렬화 할 수 있다. 특히 플랫폼 독립적인 표준 쓰레드 라이브러리인 POSIX 쓰레드를 활용하면 안드로이드나 iOS등의 다양한 스마트폰 플랫폼에서 본 방법론을 적용할 수 있다. 이의 효과적인 응용 사례로서 수백만 개의 원소를 처리하는 행렬 연산 함수를 병렬화 해보았고 실사용 환경에서 약 3배가량의 성능 향상을 확인하였다.

One of the fundamental requirements of entertainment applications is interactivity with users. The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor’s computing power, memory size and available electric power of the battery. This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or octa-core. To harness the multi-core architecture, it exploits the POSIX thread, a platform-independent thread library to be able to be used in various mobile platforms such as Android, iOS, etc. As a useful application example of the methodology, a heavy matrix calculation function was transformed to a parallelized version which showed around 2.5 ~ 3 times faster than the original version in a real-world usage environment.

There has been a snappy forward advancement in cloud. With the developing measures of affiliations, turning number of affiliations are being utilized as assets in the cloud. Issues arise regarding the certainties of various clients utilizing these assets like round measure of room associations which helps in keeping from the cost. Putting away these associations evades the high cost while posting information during the building of machine orders. This collection of information gives better execution whilst less “far point cost” and ready to make prepared modifications. Cloud can yield better possibilities through net where security weaknesses are restricted. Despite of “wellbeing” being one of the brimming with risk weakness, it adjusts unmistakable connection to go into assumed control handling general condition. This paper uses “MapReduce” library that parallelizes the figuring, and handles perplexed issues like data spread, stack modifying and adjustment to non-basic disappointment. Enormous information, spread across finished many machines, need to parallelize. Moves the data, and gives booking, adjustment to non-basic disappointment. In this paper, a graph of MapReduce programming model along with the applications are explored. The maker has delineated here the work procedure of MapReduce process. Some fundamental issues, like adjustment to non-basic disappointment, are considered in more detail. Without a doubt, even the outline of working of Map Reduce is given.

최근의 고성능 컴퓨팅 플랫폼(Latest High Performance Computing: HPC)들은 멀티코어 마이크로 프로세서 및 멀티코어 GPU (Graphic Processing unit) 같은 이질적인 칩들을 조합하여 구축되고 있으며, 그러한 이유로 이질적 HPC 플랫폼으로 불린다. 이러한 이질적 HPC 플랫폼 상에서의 응용 프로그램 병렬화는 GPU의 탁월한 부동 소수점 연산 능력을 활용하기 위해서 SIMD 방식을 주로 따르고 있다. 하지만, 이러한 방식은 이질적 HPC 플랫폼을 구성하는 중요 요소 중 하나인 범용 멀티코어 마이크로프로세서의 CPU 코어들을 병렬실행에 제대로 활용하지 못하기 때문에 가용 가능한 성능을 최대한 끌어내지 못함으로써 제한된 병렬화 방식이다. 본 논문에서는 응용 프로그램을 이질적 HPC 플랫폼 상에 매핑시키는 과정에서 가용 가능한 성능을 최대한 끌어낼 수 있도록 하는 병렬화 방법론을 제안한다. 제안하는 병렬화 방법론에서는 병렬 태스크들을 그 특징 및 계산 요구량에 따라 이질적 HPC 아키텍쳐의 구성 요소들에 적절히 분배할 수 있는 기법을 개발한다. 이를 위하여 태스크 매핑 과정에서 SIMD 방식을 넘어선 보다 보편적으로 적용 가능한 실행 모델을 활용한다.

Latest High Performance Computing (HPC) platforms are built with heterogeneous chips such as multicore microprocessors and multicore GPUs (Graphic Processing units), thus they are commonly called as Heterogeneous HPC platforms. Parallelizing applications on such platforms is mostly dominated by SIMD style of parallelism mainly to exploit GPUs’ excellent floating-point performance. However, it is a restricted parallel execution model because the multiple CPU cores are not usually participating in the parallel execution, thus the full performance potential of heterogeneous architectures is not exploited. In this paper, we propose a generalized parallelization methodology to efficiently map applications onto the heterogeneous HPC architectures in order to fully exploit their performance potential. For the methodology, we develop strategies to map parallel tasks onto different components of the heterogeneous architectures based on their application characteristics and the computing demands. A general parallel execution model beyond SIMD is adopted in the task mapping.

의료영상 데이터를 이용한 의료 시뮬레이션 시스템은 피부조직과 같은 장기의 실제 거동을 모방하기 위해 물리 연산 이 필요하다. 의료 시뮬레이션 프로그램은 크기가 큰 데이터를 사용하므로 연산 속도에 대한 제약을 받는다. 본 논 문에서는 정밀성과 속도를 적절히 고려하여 위치 기반 역학(Position Based Dynamics, PBD) 기반의 시뮬레이 션을 실행한다. 그리고 GPU 병렬 처리를 통해 PBD를 고속으로 움직임을 계산할 수 있도록, Nvidia의 CUDA C/C++를 기반으로 프로그램을 구현하였다. 병렬화 과정에서 발생하는 반복되는 커널 실행의 비효율성 문제를 스 레드 독립성을 이용하여 해결하였고, 변형체 해상도에 따른 성능 변화를 CPU와 GPU별로 비교하였다. 또한, CPU 및 GPU를 사용한 병렬 처리에서 병렬성의 한계를 검토하였다. GPU 병렬 처리를 통해 CPU 병렬 처리에서는 불가 능한 큰 변형체에 대한 시뮬레이션의 대화적 시간의 확보에 성공하였다.

A simulation system using medical image data requires calculation to imitate the actual behavior of an organ such as skin tissue. Medical simulation programs have a problem in that they take a long calculation time because they use large amounts of data. In this paper, we conducted a simulation based on Position Based Dynamics(PBD) with consideration of precision and speed. In addition, we programmed a simulation system based on Nvidia's CUDA C/C++ so that PBD can be calculated at high speed through GPU parallel processing. Using thread independence property, we addressed efficiency of iterative kernel launch in the parallelization process and we compared the performance of CPU and GPU according to the resolution of the deformable object. In addition we examined the efficiency limitations of parallel processing in CPU and GPU. With GPU parallel processing, we succeeded in securing interactive time for simulations on medical deformable object that are not possible in CPU parallel processing.

National Ministry of Manpower of Indonesia stated that statistically, the total of civil servants in January 2013 is 4,467,982 [2]. The total of regency or municipality in Indonesia, based on interior ministry of Indonesia, is 497. Therefore, the average number of civil servants in each regency or municipality is about 9909. Every year, the citizens who have been affected by taxes, including these civil servants, need to create incomes and taxes reports. This processing system was made to help the government to process all salary data for taxes income reports. In improving the speed process of this system can be done in two ways. The first way is by improving computer hardware or algorithm of this system to use effectively the existing hardware such as processor [3]. This research will observe the usage of multithread to process mass data, by considering the bottleneck effect on hard disk. An overlapping method is suggested on this research to exploit the processor resource. The analysis using mathematical method, empirical data, and visualization will be served in this research. The result of this research is that the overlapping method has improved the speed of taxes process system by showing the time reduction until 65.36%.

BDM-NBI algorithm is proposed in this paper. It focuses on the analysis of a personalized recommendation algorithm that utilizes a weighted bipartite graph suitable for processing big data. To improve the performance of this recommendation algorithm through parallel processing techniques, a sparse matrix partitioning algorithm is then developed that uses the bipartite graph as input. Our algorithm adopts bipartite graph partitioning using a vertex separator method that partitions a high-dimensional sparse matrix into a pseudo-block based diagonal matrix. Then, the recommendation algorithm analyzes all weighted sub-matrices in parallel. We produce the global recommendation weighted matrix by merging all of the sub-matrices in parallel. Experiments with Hadoop show that our algorithm has good approximation for small matrices and excellent scalability.

It becomes more and more important to design high-speed parallel cryptographic algorithms due to a growing need for information security. Conic curves cryptography is a new developing direction in the field of information security in recent years and there are less works focused on the parallel encryption algorithms for conic curves crypto system. This paper proposes four parallel algorithms for conic curves cryptosystem over finite field GF(2n). One parallel algorithm of modular-multiplication is designed by analyzing its data dependency and making some modifications of several steps. In order to figure out the average runtime, we consider the probability distributions of different cases to compute the mathematical expectation. The operations of point-addition, point-double and point-multiplication, three fundamental point operations in conic curves cryptosystem over finite field GF(2n), are paralleled based on this parallel algorithm of modular-multiplication and two parallel algorithms we proposed before. Time complexities and speedup ratios of the parallel algorithms and the sequential algorithms are calculated to make the quantitative comparison. The performance evaluation shows better efficiencies of the proposed parallel algorithms compared to the traditional algorithms.

This paper presents two parallel algorithms of basic arithmetic operations concerning multiple-precision integers over finite field GF(2n). The parallel algorithms of reduction operation and inversion-multiplication operation are designed by analyzing their data dependencies. Time complexities of the parallel algorithms and the sequential algorithms are calculated to make the quantitative comparison. The performance evaluation shows high efficiencies of the proposed parallel algorithms.

In this paper, we propose the optimized binarization in the GP-GPU. Because the binarinztion is esily paralledlized, we propose two ways of binary operations that utilize GP-GPU. The first method was to divide data load, subtraction and conversion, data store. The second method was processed collectibely. The second method was 2.52 times faster than the first method. After synthesizing the GP-GPU to the FPGA, the GP-GPU on the binarization were compared with the binarization on the ODROID XU. The binarization on the GP-GPU was 1.89 times faster than the binarization on the ODROID XU.

With more and more consumer electronics apply multi-core chips, the traditional serialized JavaScript execution engine, which is optimized by just-in-time (JIT) compilation technology, fails to utilize multi-core advantages. This paper proposes a mathematical model to detect the dependency of serial JavaScript tasks and a parallelism execution algorithm for serial JavaScript execution engines. Moreover, the parallel JavaScript execution engine with thread-level speculation technology is implemented based on the SquirrelFish Extreme engine of WebKit. As the experiment were conducted respectively on the general test platform platform Sunspider in the industry and world top 15 websites at traffic volume, the results indicate that both in the real Web application and Sunspider platform, the parallel JavaScript execution engines with 2 to 16 threads can raise the performance dramatically compared with a SquirrelFish execution engine with or without JIT acceleration, respectively.

Spatial Cluster analysis is another important technique in the field of spatial data mining, especially the K-Means spatial clustering method, which can deal with spatial objects with geographical location and attribute. However, with the development of the information society, the spatial data grows explosively, but the serial algorithm has low computing efficiency and is difficult to process massive spatial data. Aiming at spatial with a double meaning of location and attribute, the paper designed and implemented K-Means spatial clustering parallel algorithm on Hadoop. Using Yahoo Weibo user data is to do clustering analysis. Finally, the visualization of clustering results was implemented by Google Map.

In cloud computing era, automatic parallelization is still significant for virtualization platform. However, after several decades of development, the overall effect is still to be improved. Summary of the mainstream technology developments will be beneficial to reveal the future direction and trend. This paper reviews the technology of loop parallelization, which is the key issue in automatic parallelization. After introducing the basic models and approaches, we focus on the recent developments, on which we obtain the trend of this field and the conclusions about future.

Recently, computer hardware is evolving toward increasing the number of computing cores, not increasing the clock speed. In order to use the performance of parallelized hardware to the maximum, the running program must also be parallelized. However, software developers are accustomed to sequential programs, and in most cases, write programs that operate sequentially. They also have a lot of difficulty designing and developing software in parallel. We propose a method to automatically convert a sequential C/C++ program into a parallelized program, and develop a parallelization tool that supports it. It supports open multi-processing (OpenMP) and parallel patterns library (PPL) as a parallel framework. Perfect automatic parallelization is difficult due to dynamic features such as pointer operation and polymorphism in C/C++ language. This study focuses on verifying the conditions of parallelization rather than focusing on fully automatic parallelization, and providing advice to developers in detail if parallelization is not possible.

최근 다양한 국내외 기관에서 클라우드 컴퓨팅을 주목해야 할 차세대 IT 전략 기술 중 하나로 선 정하고 있다. 하지만, 클라우드 컴퓨팅 기술을 위한 다양한 연구들에서 보안기법의 부재를 확인하였 고, 강력한 보안 기법을 제공하는 것 자체가 클라우드 컴퓨팅 상용화에 있어서 가장 어려운 문제 중 하나이다. 특히, 일부 클라우드 컴퓨팅 서비스에 있어서 서버에 저장되는 데이터를 암호화하여 데이 터 기밀성을 제공하고 있지만, 이는 데이터에 대한 검색을 포함한 데이터 활용 측면에서 큰 문제를 야기할 수 있다. 이러한 문제를 해결하기 위해서 클라우드 컴퓨팅 상의 암호화된 데이터에 대해 복호 화하지 않고 연산을 수행할 수 있는 준동형 암호가 제안되었다. 준동형 암호 관련 연구는 암호 시스 템 자체에 대한 연구보다는 기존의 준동형 암호 시스템을 클라우드 컴퓨팅에 어떻게 활용할지에 더 초점이 맞춰져 있다. 이에 본 논문에서는 클라우드 컴퓨팅을 위한 준동형 암호 기법에 대한 병렬화와 병렬화된 준동형 암호 기법에 기반 한 다양한 보안 응용들에 대한 연구 방향을 도출하고자 한다.

Recently, various national and international organizations select cloud computing as one of the most important next generation IT trends. However, there are lack of cloud computing researches focused on the security and providing a strong security mechanism is one of most difficult problems to commercialize cloud computing itself. Particularly some of the data stored in the cloud server provides confidentiality by encrypting data, but this could cause problems to use data in terms of data search. To solve this problem, homomorphic encryption has been proposed to perform operations to the encrypted data without applying decryption. However, the current research on this is focused on the usage of the encryption to the cloud computing service but not on the algorithm itself. Thereby, this paper proposes the research directions of the homomorphic encryption focused on the parallelization and security application concerns.

본 논문에서는 순수 함수형 언어로 작성된 쌍방시뮬레이션 알고리듬의 성능을 멀티코어 프로세서 컴퓨터에서 병렬화로 향상시키는 방법을 연구한다. 이 병렬화에 있어 핵심 아이디어는 순수 함수형 프로그램의 참조 투명성을 십분 활용하면 병렬화가 전혀 고려되지 않고 작성된 초기 구현으로부터 최소한의 수정만으로 성능 개선 효과를 기대할 수 있다는 것이다. 초기 구현과 병렬화 구현 둘 다 순수 함수형 언어인 하스켈로 작성되었다. 초기 구현을 병렬화할 때 변화는 아주 적어서 병렬화된 구현에서도 초기 구현의 프로그램 구조가 거의 그대로 유지되었다. 벤치마크를 통해 제시된 간단한 병렬화만으로도 초기 구현과 비교해 두 배 이상의 성능 개선을 확인했다. 또한, 병렬화와는 별개의 최적화 기법인 메모이제이션이 적용된 버전의 쌍방시뮬레이션 구현에도 같은 방식의 병렬화를 적용함으로써 마찬가지로 성능을 개선할 수 있음을 확인하였다.

In this paper, we demonstrate a performance boost by parallelizing a purely functional bisimulation algorithm on a multicore processor machine. The key idea of this parallelization is exploiting the referential transparency of purely functional programs to minimize refactoring of the original implementation without any parallel constructs. Both original and parallel implementations are written in Haskell, a purely functional programming language. The change from the original program to the parallel program is minuscule, maintaining almost original structure of the program. Through benchmark, we show that the proposed parallelization doubles the performance of the bisimulation test compared to the original non-parallel implementation. We also shaw that similar performance boost is also possible for a memoized version of the bisimulation implementation.

SACOS series of subchannel analysis codes have been developed by XJTU-NuTheL for many years and are being used for the thermal-hydraulic safety analysis of various reactor cores. To achieve fine whole core pin-level analysis, the input preprocessing and parallel capabilities of the code have been developed in this study. Preprocessing is suitable for modeling rectangular and hexagonal assemblies with less error-prone input; parallelization is established based on the domain decomposition method with the hybrid of MPI and OpenMP. For domain decomposition, a more flexible method has been proposed which can determine the appropriate task division of the core domain according to the number of processors of the server. By performing the calculation time evaluation for the several PWR assembly problems, the code parallelization has been successfully verified with different number of processors. Subsequent analysis results for rectangular- and hexagonal-assembly core imply that the code can be used to model and perform pin-level core safety analysis with acceptable computational efficiency.

Inductively coupled plasma having the high-density is often used for high productivity in the plasma processing. In large area processing, the plasma can be generated by using the multi-pole connected in parallel. However, in case of this, the power cannot transfer to plasma uniformly. To address the problem, we studied the mechanism of inductively coupled plasma connected in parallel by using transformer model. We also studied about the change of the plasma parameters over the time through the power balance equation and particle balance equation.

Aho-Corasick (AC) 알고리즘은 실시간 성능을 요하는 많은 응용 분야에 적용되는 스트링 매칭 알고리즘으로서, 한번에 여러 개의 패턴들을 동시에 매칭시키는 것이 가능하다. 본 논문에서는 Intel 의 Many Integrated Core (MICO 아키텍쳐인 Xeon Phi 칩 상에서 AC 알고리즘을 병렬화한다. 이를 위하여 AC 알고리즘에서 입력 데이터에 대하여 여러 개의 패턴들을 동시에 매칭시키는 데에 사용되는 Deterministic Finite Automaton 구조를 압축시키는 새로운 기법을 제안한다. 이 기법은 캐시 미스를 감소시켜서 XeonPhi 상에서 AC 알고리즘의 성능을 크게 향상시킨다.

Aho-Corasick (AC) algorithm is a multiple patterns string matching algorithm commonly used in many applications with real-time performance requirements. In this paper, we parallelize the AC algorithm on the Intel's Many Integrated Core (MIC) Architecture, Xeon Phi Coprocessor. We propose a new technique to compress the Deterministic Finite Automaton structure which represents the set of pattern strings again which the input data is inspected for possible matches. The new technique reduces the cache misses and leads to significantly improved performance on Xeon Phi.

To speed up data-intensive programs, two complementary techniques, namely nested loops parallelization and data locality optimization, should be considered. Effective parallelization techniques distribute the computation and necessary data across different processors, whereas data locality places data on the same processor. Therefore, locality and parallelization may demand different loop transformations. As such, an integrated approach that combines these two can generate much better results than each individual approach. This paper proposes a unified approach that integrates these two techniques to obtain an appropriate loop transformation. Applying this transformation results in coarse grain parallelism through exploiting the largest possible groups of outer permutable loops in addition to data locality through dependence satisfaction at inner loops. These groups can be further tiled to improve data locality through exploiting data reuse in multiple dimensions.

이차원 팩킹 알고리즘은 메쉬 멀티프로세서 시스템을 분할 및 할당하는데 유용하게 활용될 수 있다. 기존연구에서 TP 휴리스틱 알고리즘이라 불리는 효율적인 팩킹 알고리즘을 개발하였으며 팩킹 결과가 어떻게 메쉬 멀티프로세서 시스템을 분할 및 할당하는데 활용될 수 있는지 보여주었다. 본 논문에서는 TP 휴리스틱 알고리즘의 이론적인 성능분석결과를 제시한다. 또한 알고리즘을 병렬화하여 다수의 프로세서를 이용하여 수행되었을 때 보다 적은 수행시간을 소모하게 한다.

Two-dimensional packing algorithm can be used for allocating submeshes in mesh multiprocessor systems. Previously, we developed an efficient packing algorithm called TP heuristic, and showed how the results of the packing could be used for allocating submeshes. In this paper, we present theoretical performance bounds for TP heuristic. We also present a parallel version of the algorithm that consumes reduced time when it is executed by multiple processors in mesh multiprocessors.