Earticle

Previously, Shin and colleagues (2006) reported sequential deflections of encoding-related lateralization (ERL) waveforms in event-related potentials (ERPs). One of these deflections, observed at posterior electrode sites (P7/P8), started about 400 ms poststimulus, and was dependent on both memory set-size and the degree of matching between memory-sets and test probes. These suggest that there is a level at which relations among items and degree of memory access are important in visual working memory. Based on these findings the present study investigated representational quality and degree of memory access. It was hypothesized that representational quality could be lowered by competition between stimuli (local suppression), and that degree of memory access be lowered when probes only partially match memory-set stimuli (partial matching). The relative distance (close or far) and similarity (homogeneous or heterogeneous) between memory-set stimuli were varied. ERPs were recorded while participants made old or new responses to single probes preceded by memory-sets (of size 2 or 4). ERL results obtained from 33 participants showed (a) that large ERL effects were found at the P7/P8 sites with a latency of 400-700 ms from probe onset, similar to Shin et al. (2006); (b) that significant ERL activity was observed only for the homogeneous memory-sets presented far apart; and (c) that the heterogeneous memory-sets presented nearby showed significantly smaller ERL activity than set-size 2 memory-sets (representing no-suppression and complete matching). These results support a hybrid of the local suppression and partial matching hypotheses, suggesting that representational quality and degree of memory access can jointly influence visual working memory processing.

인메모리 데이터베이스는 디스크 기반 데이터베이스를 체할 빠른 분석 처리가 가능한 메모리 기반 데이터베이스 로써 빅데이터를 처리하는데 비효율인 디스크 기반 입출력 성능을 체하는 빠른 응답 속도를 가진다. 이러한 메 모리의 활용에 따라 포식 기법에서도 메모리를 상으로 연구가 진행되고 있다. 기존의 데이터베이스 포식에서 는 데이터 추출을 해 디스크에 장된 데이터베이스 일을 주 상으로 조사하는 것을 목으로 하다. 하지만 인메모리 데이터베이스는 데이터를 메모리에 장하기 때문에 디스크 일 기반 포식으로는 데이터를 추출하지 못한다. 본 논문에서는 기존 디스크 기반 데이터베이스와는 다른 데이터 장 방식을 사용하는 인메모리 데이터베이 스의 특성을 고려하여 메모리의 수집 분석을 통해 메모리에 장된 데이터에 근 하는 방법을 제안한다. 한, 실험을 통하여 인메모리 데이터베이스에 한 메모리 포식 기법의 용 가능성을 보인다.

In-memory databases are memory-based databases allowing fast data analysis, thus replacing disk-based databases. Therefore, unlike inefficient disk-based databases, they provide fast response time allowing management of a large volume of data. As memory related studies are widely developing, recent forensic techniques have focused on memory analysis. The main purpose of the existing database forensics is to investigate the database files stored on disk for data extraction. However, it is impossible to extract data from in-memory databases by using previous forensic techniques because they store data within memory. In this paper, we propose a data access method on data stored in in-memory databases by using the collection and analysis techniques of memory data. Furthermore, we show the possibility of application of the proposed memory forensic techniques for in-memory databases through experiments.

Effective allocation of shared resources limited is a key problem for chip multiprocessors. As the processor core growth in the scale, multi thread for the shared resource limited system competition will become more intense, the performance of the system will also be more significant. In order to alleviate this problem, a fair and effective multi thread shared resources allocation scheduling algorithm is important. In all kinds of shared resources, the largest effect on the system performance is the shared cache and DRAM system. There are essential differences between the last level cache and a cache. The goal of a cache design is to provide fast data processor which requires high access speed. However, the object of the last level cache is to save data in the chip as much as possible, and the access speed requirements are not too high, it is more subject to the plate number of available transistors. Management level cache LRU strategy and its approximate algorithm are not applicable to the large capacity last level cache for traditional. It may cause destructive interference between threads, cache thrashing of stream media program lead, which will lead to a decline in the performance of processor. This paper focuses on the analysis of some hot problems of the last level cache management in the process of the large capacity of multi-core platform sharing, and puts forward the corresponding costs less.

3D 그래픽 프로세서의 시스템의 특성상 많은 수학적 계산이 요구되면서 고속처리를 위하여 GPU(Graphics Processing Unit)를 이용한 병렬처리 연구가 많이 진행되고 있다. 본 논문에서는 GPU에서 발생하는 문제점 중 캐시 메모리 미스에 의하여 발생하는 대역폭 증가와 3D 셰이더 처리 속도가 일정하지 않은 문제점을 해결하기 위하여 캐시메 모리를 사용하지 않는 병렬처리기인 MAMS를 이용한 3D 그래픽 프로세서를 제안한다. 본 논문에서 제안된 MAMS를 이용한 3D 그래픽 프로세서는 DirectX 명령 분석을 이용해 Vertex shader, Pixel shader와 Tiling 및 Rasterizing 구조를 설계 하였고, MAMS를 위한 FPGA(Xilinx Virtex6@100MHz) 보드를 구성하여, Verilog를 사용하여 설계된 구조를 개발하였다. 개발된 FPGA(100Mhz)와 nVidia GeForce GTX 660(980Mhz)의 처리시간을 확인한 결과 GTX 660를 이용한 처리 시간은 일정하지 않음을 확인하였고, MAMS를 이용한 처리 시간은 일정함을 확인하였다.

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

With the recent proliferation of memory-intensive workloads such as deep learning, analyzing memory access characteristics for efficient memory management is becoming increasingly important. Since read and write operations in memory access have different characteristics, an efficient memory management policy should take into account the characteristics of these two operations separately. Although some previous studies have considered the different characteristics of reads and writes, they require a modified hardware architecture supporting read bits and write bits. Unlike previous approaches, we propose a software-based management policy under the existing memory architecture for considering read/write characteristics. The proposed policy logically partitions memory space into the read/write area and the write area by making use of reference bits and dirty bits provided in modern paging systems. Simulation experiments with memory access traces show that our approach performs better than the CLOCK algorithm by 23% on average, and the effect is similar to the previous policy with hardware support.

VLSI(Very Large Scale Integration)와 WSI(Wafer Scale Integration)와 같은 통합기술로 인해 큰 용량의 메모리 대량생산이 가능 하게 된 지금 Redundancy는 메모리 칩의 제조와 결함이 있는 셀을 지닌 디바이스를 치료하는데 광범위하게 사용되어져왔다. 메모리칩의 밀도가 증가함에 따라 결함의 빈도 또한 증가한다. 많은 결함이 있다면 어쩔 수 없겠지만 적은 결함이 발생한 경우에는 해당 다이를 reject 시키는 것 보다는 수선해서 사용하는 것이 메모리생산 업체 입장에서는 보다 효율적이고 원가 절감 차원에서 필수적이다. 이와 같은 이유로 laser repair라는 공정이 필요하고 laser repair공정의 정확한 타깃을 설정하기 위해 redundancy analysis가 필요하게 되었다. CRA시뮬레이션은 기존의 redundancy analysis 알고리즘의 개념에서 벗어나 결함 유형별로 시뮬레이션한 후 RA를 진행함으로써 RA에 소요되는 시간을 절약함으로써 원가 경쟁력 강화를 할 수 있다.

This has been possible by integration techniques such as very large scale integration (VLSI) and wafer scale integration (WSI). Redundancy has been extensively used for manufacturing memory chips and to provide repair of these devices in the presence of faulty cells. If there are too many defects, the momory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is nedded for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The proposed CRA (Correlation Repair Algorithm) simulation, beyond the idea of the conventional redundancy analysis algorithm, aims at reducing the time spent in the process and strengthening cost competitiveness by performing redundancy analysis after simulating each case of defect.

본 논문에서는 Full 하드웨어 기반 베이스라인 프로파일 레벨 3규격 H.264 인코더 코덱에서 사용할 수 있는 Direct Memory Access (DMA)를 설계하였다. 설계된 모듈은 CMOS Image Sensor(CIS)로부터 영상을 입력받아 메모리에 저장한 후 인코더 코덱 모듈의 동작에 맞춰 원영상과 참조영상을 각각 한 매크로블록씩 메모리에서 읽어 공급 또는 저장하며, 인코더는 한 매크로블록씩 처리하는데 660 cycle이 소요된다. 설계한 구조를 검증하기 위해 JM 9.4와 같은 reference Encoder C를 개발하였으며, Encoder C로부터 test vector를 추출하여 설계한 회로를 검증하였다.

The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.

The resistive memory switching characteristics of resistive random access memory (ReRAM) using the amorphous GeSe thin film have been demonstrated at Al/Ti/GeSe/$n^+$ poly Si structure. This ReRAM indicated bipolar resistive memory switching characteristics. The generation and the recombination of chalcogen cations and anions were suitable to explain the bipolar switching operation. Space charge limited current (SCLC) model and Poole-Frenkel emission is applied to explain the formation of conductive filament in the amorphous GeSe thin film. The results showed characteristics of stable switching and excellent reliability. Through the annealing condition of $400^{\circ}C$, the possibility of low temperature process was established. Very low operation current level (set current: ~ ${\mu}A$, reset current: ~ nA) was showed the possibility of low power consumption. Particularly, $n^+$ poly Si based GeSe ReRAM could be applied directly to thin film transistor (TFT).

A spin coating process for RRAM, which is a TiN/TiO₂/FTO structure based on a PTC sol solution, was developed in this laboratory, a method which enables low-temperature and eco-friendly manufacturing. The RRAM corresponds to an OxRAM that operates through the formation and extinction of conductive filaments. Heat treatment was selected as a method of controlling oxygen vacancy (V_O), a major factor of the conductive filament. It was carried out at 100 ℃ under moisture removal conditions and at 300 ℃ and 500 ℃ for excellent phase stability. XRD analysis confirmed the anatase phase in the thin film increased as the heat treatment increased, and the Ti³⁺ and OH- groups were observed to decrease in the XPS analysis. In the I-V analysis, the device at 100 ℃ showed a low primary SET voltage of 5.1 V and a high ON/OFF ratio of 10⁴. The double-logarithmic plot of the I-V curve confirmed the device at 100 ℃ required a low operating voltage. As a result, the 100 ℃ heat treatment conditions were suitable for the low voltage driving and high ON/OFF ratio of TiN/TiO₂/FTO RRAM devices and these results suggest that the operating voltage and ON/OFF ratio required for OxRAM devices used in various fields under specific heat treatment conditions can be compromised.

Resistive random access memory (ReRAM) of metallic conduction channel mechanism is based on the electrochemical control of metal in solid electrolyte thin film. Amorphous chalcogenide materials have the solid electrolyte characteristic and optical reactivity at the same time. The optical reactivity has been used to improve the memory switching characteristics of the amorphous $As_2Se_3$-based ReRAM. This study focuses on the formation of holographic lattices patterns in the amorphous $As_2Se_3$ thin film for straight conductive channel. The optical parameters of amorphous $As_2Se_3$ thin film which is a refractive index and extinction coefficient was taken by n&k thin film analyzer. He-Cd laser (wavelength: 325 nm) was selected based on these basic optical parameters. The straighten conduction channel was formed by holographic lithography method using He-Cd laser.$ Ag^+$ ions that photo-diffused periodically by holographic lithography method will be the role of straight channel patterns. The fabricated ReRAM operated more less voltage and indicated better reliability.

대용량 고화질의 영상 응용분야에서는 많은 양의 데이터를 고속으로 처리하는 기술이 필요하며, 이를 위해 고속화된 병렬처리 시스템이 요구된다. 2004년 park은 병렬처리 메모리의 충돌 없이 여러 처리기에 데이터를 접속할 수 있는 방법을 제안하였다. 제안된 MAMS(Multi-Access Memory System) 는 이후 MAMS-PP16 및 MAMS-PP64 등으로 추가적인 연구가 이루어졌다. MAMS는 병렬처리를 위한 메모리 아키텍처로써 One-chip으로 구성되어야하기 때문에 기존 MAMS와 동일한 기능을 수행하면서 아키텍처의 최소화 하는 방법의 연구가 필요하다. 주소 계산 (ACR : Address Calculation and Routing) circuit과 MMS(Memory Module Selection)circuit의 아키텍처는 메모리에 있는 데이터를 병렬처리기(Prossing Elements)들에게 전달한다. 본 논문에서는 MMS circuit을 사용하지 않고 ACR circuit 내부에 1개의 쉬프트와 메모리 모듈의 개수만큼의 조건문으로 구성하는 방법을 통해 아키텍처를 최소화 하는 방법을 제안한다. 구현한 아키텍처의 검증을 위해 Image correlation 실험을 하였다. 실험을 통하여 제안된 MAMS-PP64의 처리시간을 측정 하였으며, 그 결과 Ratio가 평균 1.05향상 된 결과를 확인 할 수 있었다.

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

본 논문에서는 마이크로프로세서와 주변블록 사이에서 SDRAM을 사용함에 있어서 DMA(Direct Memory Access)에 의한 효율적인 SDRAM 접근방식을 제시하고 있다. 여기에서 마이크로프로세서는 AMBA 버스를 통해서 SDRAM에 접근을 하고 DMA는 DMA 전용 버스를 통해서 SDRAM에 접근한다. 마이크로프로세서가 SDRAM에 접근하지 않고 다른 레지스터에 접근하거나, 아니면 마이크로프로세서 캐쉬에서 히트(hit)신호가 발생하여 SDRAM에 접근할 필요가 없을 때에 주변 블록에서는 DMA를 통해서 SDRAM에 접근하여 데이타를 읽거나 쓰기 동작을 통해서 SDRAM을 효율적으로 사용할 수 있다. 이 방법은 DMA가 마이크로프로세서의 SDRAM 억세스를 최소한의 방해로 SDRAM을 사용할 수 있다. 이와 같은 방법을 이용함으로써 전체적인 시스템 효율을 높여 약 16.8% 정도의 성능 향상 효과를 가져옴을 확인 할 수 있었다.

In this paper, we present the efficient way of SDRAM accessing through the DMA(Direct Memory Access) when a microprocessor and peripheral blocks are sharing a SDRAM. The microprocessor is able to access a memory through the AMBA which is the system bus provided by ARM Corporation and DMAs are able to access a memory through their own bus. Peripheral block's reading and writing on the SDRAM memory are realized by the intermediate DMA in order to minimize times of access and addressing the memory. While the microprocessor doesn‘t access to the SDRAM aproaching other registers or occurring a hit signal for fetching program or data, the DMAs may read/write the data in the SDRAM without an interference of the AMBA. This way increases the efficient of the system and performance is more by 16.8%.