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Research on the Management Strategy of the Last Level Cache Sharing Multi-Core Processor

첫 페이지 보기
  • 발행기관
    보안공학연구지원센터(IJGDC) 바로가기
  • 간행물
    International Journal of Grid and Distributed Computing 바로가기
  • 통권
    Vol.8 No.5 (2015.10)바로가기
  • 페이지
    pp.287-302
  • 저자
    Yuhuai Wang, Huixi Zhang, Yaping Sun, Qihui Wang
  • 언어
    영어(ENG)
  • URL
    https://www.earticle.net/Article/A257208

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원문정보

초록

영어
Effective allocation of shared resources limited is a key problem for chip multiprocessors. As the processor core growth in the scale, multi thread for the shared resource limited system competition will become more intense, the performance of the system will also be more significant. In order to alleviate this problem, a fair and effective multi thread shared resources allocation scheduling algorithm is important. In all kinds of shared resources, the largest effect on the system performance is the shared cache and DRAM system. There are essential differences between the last level cache and a cache. The goal of a cache design is to provide fast data processor which requires high access speed. However, the object of the last level cache is to save data in the chip as much as possible, and the access speed requirements are not too high, it is more subject to the plate number of available transistors. Management level cache LRU strategy and its approximate algorithm are not applicable to the large capacity last level cache for traditional. It may cause destructive interference between threads, cache thrashing of stream media program lead, which will lead to a decline in the performance of processor. This paper focuses on the analysis of some hot problems of the last level cache management in the process of the large capacity of multi-core platform sharing, and puts forward the corresponding costs less.

목차

Abstract
 1. Introduction
 2. The Relevant Thoery Of Cache
 3. The Optimization Of Cache Management Strategy
 4. The Cache Verification Design And Simulation Platform
 5. Experimental Results
 6. Conclusions
 Acknowledgements
 References

키워드

Chip multiprocessor last level cache cache partitioning Memory access

저자

  • Yuhuai Wang [ Qianjiang College, Hangzhou Normal University, Hangzhou 310036, China ] Corresponding author
  • Huixi Zhang [ Qianjiang College, Hangzhou Normal University, Hangzhou 310036, China ]
  • Yaping Sun [ Qianjiang College, Hangzhou Normal University, Hangzhou 310036, China ]
  • Qihui Wang [ Qianjiang College, Hangzhou Normal University, Hangzhou 310036, China ]

참고문헌

자료제공 : 네이버학술정보

간행물 정보

발행기관

  • 발행기관명
    보안공학연구지원센터(IJGDC) [Science & Engineering Research Support Center, Republic of Korea(IJGDC)]
  • 설립연도
    2006
  • 분야
    공학>컴퓨터학
  • 소개
    1. 보안공학에 대한 각종 조사 및 연구 2. 보안공학에 대한 응용기술 연구 및 발표 3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최 4. 보안공학 기술의 상호 협조 및 정보교환 5. 보안공학에 관한 표준화 사업 및 규격의 제정 6. 보안공학에 관한 산학연 협동의 증진 7. 국제적 학술 교류 및 기술 협력 8. 보안공학에 관한 논문지 발간 9. 기타 본 회 목적 달성에 필요한 사업

간행물

  • 간행물명
    International Journal of Grid and Distributed Computing
  • 간기
    격월간
  • pISSN
    2005-4262
  • 수록기간
    2008~2016
  • 십진분류
    KDC 505 DDC 605

이 권호 내 다른 논문 / International Journal of Grid and Distributed Computing Vol.8 No.5

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