Earticle

In today’s technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. To overcome bottleneck of communication system, NOC is an upcoming archetype. In on-chip network, router is considered as an important component. This paper proposes router, its components and parameters which affects the entire design. Thus, to validate the functioning of NOC on hardware, router has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.

In this work, we report a detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA).The designing of this memory circuit is done by Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA. Different RAM styles and RAM extracts are compared on basis of power consumption and reduction. Auto RAM style is the default RAM style and it consumes minimum power as compared to block RAM. The RTL schematic shows I/O ports, nets and primitives. Bufgdll also consumes less power and power reduction is also maximum for bufdll and auto RAM as compared to block RAM, ibufg and RAM extract yes. Auto RAM at 10GHz frequency can be used in designing various applications like in radio astronomy, microwave devices and communications, wireless LAN, most modem radars, communications satellites, satellite television broadcasting.

Field-Programmable Gate Array (FPGA)기반 탭-딜레이 방식의 시간-디지털 변환기에서 해상도는 FPGA 내부 지연소자의 지연시간에 의존하여 해상도를 향상시키는데 한계가 있다. 또한 각 지연소자의 단위 지연시간(bin width)의 불균일성 때문에 정확도가 저하되는 문제점이 있다. 따라서 두 개의 캐리체인을 단위 지연시간의 절반만큼의 차이를 두고 나란히 배치하여 각각의 출력을 모두 사용하여 해상도를 향상시키는 방법을 제안한다. 제안한 방법은 두 개의 캐리체인상의 효과적인 bin 재배치를 통해 ultra wide bin 및 narrow bin의 사용을 제한할 수 있어서 정확도 향상에도 기여한다. 이 방식은 내부 캐리체인 자원을 두 배로 사용해야 한다는 문제점이 있지만 파인 입력부에서 클럭의 up edge와 down edge 중 측정범위를 줄일 수 있는 edge를 선택하게 하여 파인부의 측정 범위를 클럭의 반주기로 줄임으로써 해결한다. 제안한 시간-디지털 변환기의 성능 측정결과 해상도는 13.02ps에서 8.802ps로 향상되었고, INL(Integral Nonlinearity)은 기존 -27.979~19.283ps에서 -11.557~16.274ps로, DNL(Differential Nonlinearity)은 -7.981~29.022ps에서 -5.879~13.123ps로 향상되었다.

In a field-programmable gate array (FPGA)-based tapped-delay-line time-to-digital converter, the delay time of the delay element integrated in the FPGA sets the resolution limit and non-uniformity of the delay time decreases the accuracy. In order to improve the timing resolution in a given FPGA, this study proposes a dual-tapped-delay-type time-to-digital converter (TDC), in which two carry chains are arranged side by side with a finely controlled time difference. By employing effective bin arrangement of the two carry chains, ultra wide or narrow bins are excluded, which improves the measurement accuracy. The selection of the reference clock edge between the up and down edges reduces the required length of carry chains and, consequently, compensates for increase in the consumption of FPGA resources due to the application of dual carry chains. The average resolution of the proposed TDC was improved from 13.02ps to 8.802ps and the integral non-linearity (INL) and diff erential non-linearity (DNL) were improved from -27.979~19.283ps to -11.557~16.274ps and from -7.981~29.022ps to -5.879~13.123ps, respectively.

Field-programmable gate array (FPGA) 기반 시간-디지털 변환기 (time-to-digital converter: TDC)는 구조가 단순하고, 빠른 변환속도를 갖는 딜레이 라인 (delay-line) 방식을 주로 사용한다. 하지만 딜레이 라인 방식 TDC의 시간 측정범위를 늘리기 위해서는 딜레이 라인의 길이가 길어지므로 사용되는 소자가 많아지고, 비선형성으로 인한 오차가 증가하는 단점이 있다. 따라서 본 논문은 동일한 길이의 딜레이 라인에 펄스 트레인 (pulse-train)을 입력하여 시간 측정범위를 향상시키고, 리소스를 효율적으로 사용하는 방식을 제안한다. 펄스 트레인 입력 방식의 TDC는 긴 시간을 측정하기 위하여 시작신호의 입력과 동시에 4-천이 (transition) 펄스 트레인이 딜레이 라인에 입력된다. 그리고 동기회로 (synchronizer) 대신 천이 상태 검출부를 설계하여 중지신호 입력 시 사용된 천이를 판별하고, 준안정 상태 (meta-stable state)를 피하면서 딜레이 라인의 길이를 줄이는 구조를 갖는다. 제안한 TDC는 72개의 딜레이 셀 (delay cell)을 사용하였고, 파인부 (fine interpolator)의 성능 측정 결과, 시간 측정범위는 5070 ps, 평균 분해능은 20.53 ps, 최대 비선형성은 1.46 LSB였으며, 시간 측정범위는 계단 (step) 파형을 입력신호로 사용하는 기존 방식 대비 약 343 % 향상되었다.

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

Field programmable gate array 기반 시간-디지털 변환기(Time to Digital Converter)로 가장 널리 사용되는 딜레이 라인(tapped delay line) 방식은 딜레이 라인의 길이가 길어지면 정확도가 떨어지는 단점이 있다. 이에 본 논문에서는 동일한 시간 해상도를 가지면서 딜레이 라인의 길이를 줄일 수 있도록 4 위상 클럭을 사용하고 이중 상태 판별 제어부를 가지는 시간-디지털 변환기 구조를 제안한다. 4 위상 클럭 별로 딜레이 라인 구성 시 발생하는 라인 간 딜레이 오차를 줄이기 위해 입력신호와 가장 가까운 클럭과의 시간 차이만 하나의 딜레이 라인으로 측정하고 어떤 위상 클럭이 사용되었는지를 판별하는 구조를 가졌다. 또한 싱크로나이저 대신 이중 상태 측정 state machine을 이용하여 메타스태이블을 판별함으로써, 싱크로나이저로 인한 딜레이 라인의 증가를 억제하였다. 제안한 시간-디지털 변환기(TDC)의 성능 측정 결과 1 ms의 측정 시간 범위에 대해 평균 분해능 22 ps, 최대 표준편차 90 ps을 가지며 비선형성은 25 ps였다.

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

탭 딜레이(tapped delay) 방식은 field-programmable gate arrary(FPGA) 내부 리소스를 이용한 설계에 적합하여 FPGA기반 시간-디지털 변환기(time-to-digital converter)로 널리 사용되고 있다. 그런데 이 방식의 시간-디지털 변환기에서는 지연 소자로 사용하는 전용 캐리체인(dedicated carry chain)의 탭 당 지연시간 차이가 정밀도 저하의 가장 큰 원인이 되고 있다. 본 논문에서는 일반적인 구형파 대신 고정된 시간 폭을 가지는 펄스신호를 지연 소자로 인가하고 상승과 하강 엣지에서 두 번의 시간 측정을 통해 전용 캐리체인내 지연시간의 불균일성을 보상하고 정밀도를 향상하는 시간-디지털 변환기 구조를 제안한다. 제안한 구조는 두 번의 시간 측정을 위해 2개 구역의 전용 캐리체인을 필요로 한다. Dual 엣지 보상 전 두 전용 캐리체인에서 탭 당 지연시간의 평균은 각각 17.3 ps, 16.7 ps에서 보상 후 평균은 11.2 ps, 10.1 ps으로 감소하여 각각 35%, 39% 이상 향상되었다. 가장 중요한 탭 당 최대지연 시간은 41.4 ps, 42.1 ps에서 20.1 ps, 20.8 ps 로 50% 이상 감소하였다.

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of $100{\times}100mm^2$ with 0.5 mm interval) to 87.5% (scanning of $200{\times}200mm^2$ with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

The application of the Internet of Things generates massive end-device data. Traditional end-to-edge data caching methods lack parallelism, consume numerous resources, and lack data backup mechanisms. We propose a lightweight high-speed data caching and forwarding architecture based on a field-programmable gate array. In the basic scheme, a double-data-rate memory read/write mixed control method is proposed to efficiently cache massive amounts of data. To improve reliability, we propose address-space virtualization to forward data to backup devices. To satisfy the demand for higher performance scenarios, we propose a real-time data shunting mechanism to realize an optimized scheme that supports higher data rates. These two schemes support single-link high-speed data caching and forwarding at 10 and 40 Gbps. Compared with the existing method, the basic and optimized schemes improve the performance by 25% and four times and save 66% and 40% of the resources, respectively. Thus, we provide a lightweight and reliable high-performance end-to-edge data caching solution for resource-constrained edge devices.