Earticle

초록

영어

In today’s technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. To overcome bottleneck of communication system, NOC is an upcoming archetype. In on-chip network, router is considered as an important component. This paper proposes router, its components and parameters which affects the entire design. Thus, to validate the functioning of NOC on hardware, router has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.

목차

Abstract
 1. Introduction
 2. Literature Survey
 3. NOC Router
 4. Results and Discussions
 5. Conclusion
 6. Future Work
 References

키워드

저자

• Gaurav Verma [ Department of Electronics & Communication, Jaypee University, India ]
• Harsh Agarwal [ Department of Electronics & Communication, Jaypee University, India ]
• Shreya Singh [ Department of Electronics & Communication, Jaypee University, India ]
• Shaheem Nighat Khanam [ Department of Electronics & Communication, Jaypee University, India ]
• Prateek Kumar Gupta [ Department of Electronics & Communication, Jaypee University, India ]
• Vishal Jain [ Bharati Vidyapeeth's, Institute of Computer Applications and Management (BVICAM), INDIA ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Future Generation Communication and Networking

• 간기

  격월간

• pISSN

  2233-7857

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605