Earticle

초록

영어

In this work, we report a detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA).The designing of this memory circuit is done by Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA. Different RAM styles and RAM extracts are compared on basis of power consumption and reduction. Auto RAM style is the default RAM style and it consumes minimum power as compared to block RAM. The RTL schematic shows I/O ports, nets and primitives. Bufgdll also consumes less power and power reduction is also maximum for bufdll and auto RAM as compared to block RAM, ibufg and RAM extract yes. Auto RAM at 10GHz frequency can be used in designing various applications like in radio astronomy, microwave devices and communications, wireless LAN, most modem radars, communications satellites, satellite television broadcasting.

목차

Abstract
 1. Introduction
 2. Literature Review
 3. Block Diagram
 4. Power Consumption in a 16-bit Memory Circuit
 5. Conclusion
 6. Future Scopes
 References

키워드

저자

• Inderpreet Kaur [ Department of Electronics and Communications Chitkara University, Punjab, India School of Engineering Deakin University, Australia ]
• Lakshay Rohilla [ Department of Electronics and Communications Chitkara University, Punjab, India School of Engineering Deakin University, Australia ]
• Alisha Nagpal [ Department of Electronics and Communications Chitkara University, Punjab, India School of Engineering Deakin University, Australia ]
• Abhishek Gupta [ Department of Electronics and Communications Chitkara University, Punjab, India School of Engineering Deakin University, Australia ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605