Earticle

본 연구는 시간-보간법을 적용한 FLASH analog-to-digital converter (ADC)에 관한 것이다. 시간-보간 법은 기존의 FLASH ADC에서 요구되는 전압영역 비교기의 개수를 줄일 수 있으며 이 따른 전력 소모 및 칩 면적 의 절약을 기대할 수 있다. 본 연구에서는 5-bit, 즉 31개의 양자화 레벨을 갖는 ADC를 설계 및 구현하였으며, 16개의 양자화 레벨은 기존의 전압영역 비교기 방식을 유지하고, 나머지 15개의 양자화 레벨은 시간영역 비교기 를 통하여 처리되도록 구성하여, 기존 5-bit FLASH ADC 대비 전압영역 비교기의 숫자를 48.4% 줄일 수 있었다. 시제품은 14 nm Fin Field-effect transistor (FinFET) 공정으로 제작되었으며 구현면적은 0.0024 mm2, 전력 소모는 0.8 V 전원전압에서 0.82 mW로 측정되었으며, 400 MS/s의 변환속도 21 MHz 정현파 입력에 대하여 ADC는 28.03 dB의 신호-대-잡음비 (SNDR), 즉 4.36 유효비트(ENOB)의 성능을 보였다.

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

In this paper, modified architecture of CMOS capacitive fingerprint sensor readout circuit is presented for general type of a switched capacitive integrator scheme. The proposed architecture supports wide and flexible operation range without ADC. It also operates faster than a typical integrator scheme for one frame image capture. The circuit includes an analog comparator in each pixel and counters. The referenced analog voltage of each sensor cell is controlled by an external or internal bias.

A Boolean Combinational circuit can be made of some wires and logic gates whose outputs at any time are determined directly from the present combination of inputs without any regard to previous input. Reduction of number of gates (area) and the length of the signal path (delay) to optimize a Boolean circuit is always an overriding concern in the design of digital integrated circuit. The accepted phenomena that combinational circuit is based only on acyclic (loop-free or feed-forward) topology no longer exist. Introducing cycles in combinational circuit we may have same acyclic operation with reduced area and delay of the circuit. Cyclic circuits that do not hold state or oscillate are often the most convenient representation for certain functions, such as arbiters. The main aim of cyclic circuit is to introduce structural feedback & to avoid the logical feedback in order to get combinational primary output. In this survey, we advocate the technological depth of cyclic circuit and their design methodologies with certain merits and demerits. It includes functional analysis i.e. to determine what values will appear and the timing analysis which determine when these values will appear.

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS flash ADCs for SoC applications. In this paper an area efficient low power high Speed 3-bit Flash Type ADC using bit referenced encoder is proposed in 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is also introduced as a modification of the conventional comparator. The proposed design of the ADC occupies an active area of 0.0036 mm2 and consumes 43.146 μW of Average Power while operating with an input frequency (fin) of 10 MHz and a supply voltage of 1.8 Volt.

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

본 본문은 NOMS 와 CMOS 집적회로에서 발생 가능한 물리적 결점에 의한 결함에 대해서 Fail-safe 시스템에서 사용할 목적이며, 첫 번째 VLSI 회로 상에서 다양한 물리적 결점을 반영할 수 있는 PLA에 대한 결함 모델을 제시한다. PLA에 근거한 설계 이유는 VLSI칩에서의 물리적 결점을 세부적으로 분식하는 것이 너무 복잡하기 때문이다. 두 번째 본문에서는 2단 AND-OR 또는 NOR-NOR 회로로 구현한 설계가 최적의 크기를 갖는다는 것을 보여준다. 또한 NOR-NOR PLA로 구현한 비교기가 제시한 단일 결함 모델에 대해서 자체시험성을 갖는다는 것을 증명한다. 최종적으로 Fail-safe 가산기에 대해 빌딩블럭으로 자체시험 비교기의 적용을 논한다.

This paper presents the implementation of comparator which are Fail-Safe with respect to faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it at the Fail-Safe system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper show that these design, which was implemented with 2 level AND_ORor NOR-NOR circuit, are optimal in term of size. And it also present a formal proof that a comparator implemented as NOR-NOR PLA, based on these design, is self-testing with respect to most single faults in the presented fault model. Finally, it discuss the application of the self-testing comparator as a building block for implementing Fail-Safe Adder.

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

High-speed device is essential to optoelectric IC for optical storage system such as CD-ROM, DVD, and to ADC for high-speed communication system. This paper represents the BiCMOS process which contains high-speed SAVEN bipolar transistor and analyzes the frequency and switching characteristics of it briefly. Finally, to prove that the SAVEN device is adequate for high-speed system, latched comparator operating at 500MHz is designed with the SPICE parameter extracted from BiCMOS device simulation.

Applying the price sales ratio (PSR) valuation, our case study examines the validity of the relative valuation of the stock of a Korean case company Cafe 24, which reported losses and unrealized profits, but listed its stock on the KOSDAQ market via the Tesla listing channel. We find that the PSR method evaluates the stock prices of the case company, which vary significantly depending on the selection of comparable companies. When selecting foreign companies with different risk-free interest rates and capital market structure from the target company, or domestic comparable companies with a heterogeneous business or sales structure, the price per share of the case study (using the PSR relative valuation) is different from its initial public offering price. Although this study is not yet widely used as a valuation method for unlisted stocks that are expected to have future growth potential, such as platform companies or innovative companies in Korea, we examine the PSR, which is actively used in foreign countries. This study provides financial managers, financial analysts, and researchers with invaluable information on the importance of selecting appropriate comparable companies at the PSR relative valuation for Tesla listing of innovative companies.

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

중성자 방사화 및 방사능 계측에 관계하는 핵데타를 세밀히 연구검토하여 망간을 불순물로 함유하고 있는 철선을 단일비교체로 한 중성자 방사화분석법을 발전시켰다. 유효반응 단면적의 변화를 원자로 내부 스펙트럽의 열외 중성자의 비율과 같은 스펙트럼 지표 및 그 외 다른 변수의 함수로 검토하였으며 조사위치에서 중성자 스펙트럽의 변위로 생기는 오차를 토의하였다. 각원소의 이미 아는양을 취하여 단일비교체와 함께 조사한 다음 본법에 의해서 그 함량을 산출하여서 원래 취한 양과 비교하였다. 그 결과 우연오차는 일반적인 비교법으로 얻은 오차보다 크지 않았으나 계통적 오차는 대략 20%이내였다. 본법을 모나자이트 중에 함유된 14개 희토류 원소의 정량과 표준배추시료 중에 있는 다른 7개의 원소정량에 적용하였다. 그 결과 분석치는 만족할만한 재현성을 나타내었으며 종래의 비교법으로 얻을 수 있는 정도의 정착성으로 이들 원소를 분석할 수 있었다.

A method of activation analysis, based on the irradiation and counting of an iron wire which contains manganese impurity as the single comparator. has been elaborated by critical evaluation of nuclear data involved in activation and activity measurement. The variation of effective cross section is investigated as a function of the spectral index and other parameters such as a measure of the proportion of epithermal neutrons in the reactor spectrum. The errors induced by shifts in the neutron spectrum in the irradiation positions are discussed. The known amount of each element is irradiated simultaneously together with the single comparator, and the obtained values are compared with the known amount of each element. The results show that en general the random errors are not greater than those obtained by using the conventional relative method, but the systematic errors were up to about 20%. This method is applied to the determinations of fourteen rare earth elements in monazite as well as other seven elements in the standard kale powder. The satisfactory reproducibility of the present method makes possible the determination of the elements with an accuracy attainable with the conventional relative method.

Background and Purpose Oral administration of cholinesterase inhibitors is often associated with adverse gastrointestinal effects, and so developing an alternative administration route, such as transdermal, is urgently needed. The primary objective of this study was to determine the efficacy and safety of the IPI-301 donepezil transdermal patch compared with donepezil tablets (control) in mild-to-moderate probable Alzheimer’s disease (AD). Methods This prospective, randomized, double-blind, double-dummy, two-arm parallel, multicenter trial included 399 patients, among whom 303 completed the trial. For randomization, the patients were stratified based on previous treatment and donepezil dose; patients in each stratum were randomized to the test and control groups at a 1:1 ratio. Results The difference between the control group and the IPI-301 group, quantified as the Hodges?Lehmann estimate of location shift, was 0.00 (95% confidence interval: -1.00 to 1.33), with an upper limit of less than 2.02. The change in Alzheimer’s Disease Cooperative Study? Activities of Daily Living (ADCS-ADL) score differed significantly between the IPI-301 and control groups (p=0.02). However, the changes in the full-itemized ADCS-ADL scores at week 24 did not differ significantly between the two groups. There were no differences between the two groups regarding the scores for the Clinician Interview-Based Impression of Change (p=0.9097), Mini-Mental State Examination (p=0.7018), Neuropsychiatric Inventory (p=0.7656), or Clinical Dementia Rating (p=0.9990). Adverse events, vital signs, and laboratory test results were comparable between the two groups. Conclusions IPI-301 was safe and efficacious in improving cognitive function in patients with mild-to-moderate AD.

In this paper, a single-inductor multiple-output (SIMO) DC-DC converter with comparator based feedback circuit is proposed. The proposed SIMO converter does not need feedback loop which is composed of error amplifier or OTA and its compensation network. Therefore, tolerance of the feedback loop is improved since it does not suffer the variation of compensation resistor and capacitor. Also, variation of loop characteristic arises from external inductor value, capacitor value and load current can be removed. The measured peak power conversion efficiency is 81% when the output power is 140mW.

The spectral responsivity of solar cells has been measured under high background irradiance using an LED-based differential spectral responsivity Comparator (DSR-C). The comparator developed is fully automated and has some advantages: It does not need a chopper to modulate the light. Unlike the conventional method, it does not require a monochromator to select wavelength. It covers a wavelength range up to 1200 nm. The wavelength range of the comparator is limited by the spectral power distribution of the LEDs and the spectral responsivity of the standard detector. An active temperature control was utilized to meet the specified standard conditions of solar cell test. This work shows the effect of different levels of background irradiance on the spectral responsivity and the importance of same background irradiance for solar cell test as specified by the corresponding standard.

Purpose: To compare the effectiveness of the magnesium (Mg)-enriched formula vs. control formula in constipated infants. Methods: An open-label, interventional, and the comparator-controlled study was conducted to evaluate the effectiveness of the Mg-enriched formula in formula-fed infants ${\leq}6$ months old presenting with functional constipation according to modified Rome IV criteria. Infants were randomized 1:1 to intervention or control formula for 30 days. Parents recorded stool consistency (hard, normal, or watery) and frequency on days 1-7 and 23-29. Physicians recorded patient baseline characteristics and performed the clinical examination at the time of three patient visits (baseline, day 8, and 30). Results: Of the 286 recruited infants, 143 received the Mg-rich formula and 142 received the control formula. After 7 days, significantly more infants had stools with normal consistency with the Mg-rich formula compared to the infants fed with the control formula (81.8% vs. 41.1%; p<0.001). The number of infants passing one or more stools per day was increased at day 7 in the Mg-rich formula group (86.7% vs. 68.2%; p<0.001). At days 7 and 29, >25% of infants responded completely to the Mg-rich formula compared to <5% of infants fed with the control formula (p<0.001). Parents of infants in the Mg-rich formula group were very satisfied with the treatment (80.8% vs. 10.2%), with the majority willing to continue treatment after 30 days (97.9% vs. 52.6%; p<0.001). Conclusion: The Mg-rich formula significantly improved stool consistency and frequency compared to the control formula in constipated infants.