Earticle

초록

영어

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS flash ADCs for SoC applications. In this paper an area efficient low power high Speed 3-bit Flash Type ADC using bit referenced encoder is proposed in 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is also introduced as a modification of the conventional comparator. The proposed design of the ADC occupies an active area of 0.0036 mm2 and consumes 43.146 μW of Average Power while operating with an input frequency (fin) of 10 MHz and a supply voltage of 1.8 Volt.

목차

Abstract
 1. Introduction
 2. Related Work
 3. Blocks of the Proposed ADC
  3.1. TMCC
  3.2. Bit Reference Encoder
  3.3 Proposed Flash Type ADC Architecture
 4. Results and Discussions:
  4.1. Differential Non- Linearity and Integral Non- Linearity
  4.2. Missing Codes
  4.3 Observations
 5. Conclusion
 References

키워드

저자

• Aditi Kar [ Department of ETCE, Tripura Institute of Technology Agartala -791112 ]
• Alak Majumder [ Department of ECE, National Institute of Technology, Arunachal Pradesh, Yupia – 799009, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605