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HIGH SPEED, LOW COMPLEXITY, FOLDED, POLYMORPHIC WAVELET ARCHITECTURE USING RECONFIGURABLE HARDWARE

R.Lavanya, Saranya B

보안공학연구지원센터(IJAST) International Journal of Advanced Science and Technology vol.18 2010.05 pp.23-30

※ 원문제공기관과의 협약기간이 종료되어 열람이 제한될 수 있습니다.

The main aim of this paper is to design and implement a high speed, low complexity and polymorphic architecture for reconfigurable folded wavelet filters. 5/3 wavelet results are incorporated into the 9/7 data path which reduces the number of adders compared to other solutions and also allows on the fly switching between the filters. The proposed work is to improve the speed of this reconfigurable architecture. This is accomplished by scheduling. A weight based scheduling algorithm has been used in this paper. This is an analysis method to improve inter task communication as well as data dependencies among tasks which will reduce the overall communication overhead and processing time.

 
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