Earticle

This paper presents a quantum-dot cellular automata (QCA) 3-8 decoder with low hardware complexity. The proposed architecture is based on inverter chains to get inverse value and cross over a wire. We also use 5-input majority voting gates for 3-input AND gates. In this paper, we focus on the hardware complexity to reduce the number of cells and minimize wasting an area. Our architecture has not only an excellent regularity and scalability but a strong signal strength so that it is easy to extend a structure and connect with other circuit.

This paper presents a 2-to-1 multiplexer based on quantum-dot cellular automata(QCA) with low hardware complexity. A QCA is the computing with cellular automata composed of arrays of quantum-dot devices. We propose a novel 2-to-1 multiplexer using three NAND gates in QCA. We focus on reducing a hardware complexity and minimizing a wasted cell. In order to the implementation of the 2-to-1 multiplexer, we use a new equation using De Morgan’s law. Our new architecture also can increase the speed with clock phase.

The main aim of this paper is to design and implement a high speed, low complexity and polymorphic architecture for reconfigurable folded wavelet filters. 5/3 wavelet results are incorporated into the 9/7 data path which reduces the number of adders compared to other solutions and also allows on the fly switching between the filters. The proposed work is to improve the speed of this reconfigurable architecture. This is accomplished by scheduling. A weight based scheduling algorithm has been used in this paper. This is an analysis method to improve inter task communication as well as data dependencies among tasks which will reduce the overall communication overhead and processing time.

In this paper, we present the block diagonalization (BD) algorithm for the multiple-user multiple input multiple output (MU-MIMO) $4{\times}4$ system using specific purpose processor (SPP) hardware. Our objective is to improve the single-user MIMO (SU-MIMO) system using the MU-MIMO technology, which is remarkably fast and allows more users to connect simultaneously. To that end, our MU-MIMO precoder uses the BD algorithm to ensure signal integrity when connecting multiple users; but remains accurate and stable. However, a precoder that uses the BD algorithm is computationally complex; therefore, we use an SPP with special functions designed to compute the BD algorithm. The implementation test results show that our SPP computes the BD algorithm faster than the software solution.

In this paper, a high-performance, low-area gradient-magnitude calculator architecture is proposed, based on approximate image processing. To reduce the computational complexity of the gradient-magnitude calculation, vector properties, the symmetry axis, and common terms were applied in a hardware-resource-shared architec-ture. The proposed gradient-magnitude calculator was implemented using an Altera Cyclone IV FPGA (EP4CE115F29) and the Quartus II v.16 device software. It satisfied the output-data quality while reducing the logic elements by 23% and the embedded multipliers by 76%, compared with previous work.

A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

This paper presents an efficient hardware architecture of demodulating fingers to demodulate the multi-path propagating signals in MC-CDMA Mobile System. We design a new architecture of demodulating fingers which share the single arithmetic unit to reduce the hardware complexity. This arithmetic unit performs MAC(Multiplication and Accumulation) operations of all demodulating fingers. The proposed architecture is suitable for Is-95 based CDMA PCS system. Three demodulating fingers for MC-CDMA which demodulate 7 channels contain about 42K logic gates. Our proposed system is shown to be very useful for Multi-Code CDMA system in which several channels are demodulated simultaneously.

본 논문에서는 FDS를 응용한 하드웨어 분할 방법을 강 제약 조건을 만족하면서 FDS를 응용하는 방법보다 낮은 복잡도의 분할 알고리즘을 제안한다. 기존의 FDS 응용 방법은 힘값 계산에서 종속성에 의해 후위 연산이 받는 영향값을 계산하여야 하므로 이로 인한 시간 복잡도가 가중되었다. 본 논문에서는 이러한 복잡도를 저하시키기 위해 노드의 분포 그래프와 구현에 소요되는 비용, 그리고 해당 파티션에서의 실행시간 등에 의해 상대적 긴박도를 정의하여 분할을 수행하지만, 종속성 검사는 종속성 제약조건에 의한 분포그래프의 변화와 스케쥴에 대해서만 고려되며 힘값 계산에는 고려하지 않는다. 또한, 분할 단계에서 스케쥴링을 함께 고려함으로써 합성 이후에 재 스케쥴링의 부하를 경감할 수 있도록 하였다. 제안 알고리즘 결과는 ILP 결과와 비교 분석하였다.