Earticle

In the packet based systems for supporting burst data traffic networks, the fast synchronization is required in the short period of time upon receiving the data frame at the receiver. This important operation is generally carried out at the header part of the packet which is usually called the preamble. While detecting the existence of the valid signal frame through the carrier sensing it is also important to adjust the signal level at the input of the baseband blocks. This is generally called automatic gain control and it is essential to minimize the processing time for the gain decision for incoming received signals. In this paper, target level of the AGC is determined based on the bit-error-rate (BER) performance and SQNR for the varying power of the AGC input signal. The other parameters are optimized by utilizing statistics of the incoming signal including the degree of saturation as well as the incoming signal power. The proposed optimization method provides the improved convergence speed which in turn results in the reduced processing time.

The variable integral gain voltage and current double closed-loop control technique based on a PWM inverter is studied in this paper. To improve the response speed and steady-state accuracy of the system, the voltage and current double closed-loop control model is established at first, and then the fixed integral of double closed-loop control strategy is analyzed based on this model. Because variable integral gain control method can improve the control precision based on the double closed loop, the voltage and current double closed-loop control strategy with variable integral gain is proposed. Finally, a series of simulation and experiment results are accomplished to verify the validity of this method. It is shown that the dynamic response time is 2ms and the maximum voltage change rate is only at 0.5%, and the steady-state accuracy can reach 99.55%.

This paper presents a fractional gain-control technique for a digitally controlled oscillator (DCO). The proposed fine-fractional gain-control scheme improves the jitter performance by suppressing the nonlinear effect of a bang-bang digital phase-locked loop (BB-DPLL). In addition, the proposed structure significantly reduces the chip area, because the proposed fractional DCO dithering circuit requires only one accumulator with an N-2-bit width, while conventional topologies require multiple accumulators with N-bit widths. The simulation result shows that the period jitter of the proposed structure (0.83 ps) is three times better than that of a digital PLL based on a conventional second-order sigma-delta modulator (2.58 ps).

In this paper a closed-form predictive control which takes the intervalwise receding horizon strategy is presented and its stability properties are investigated. A slate-space form output predictor is derived which is composed of the one-step ahead optimal output prediction, input and output data of the system. A set of feedback gains are obtained using the dynamic programming algorithm so that they minimize a multi-stage quadratic cost function and they are used periodically.

PI controllers are one of the most widely used controllers in industrial control systems due to their simple algorithms and stability. The parameters K_p and K_i determine the performance of the system response. The response is expected to improve by increasing the gain of the PI controller. However, too large a gain will accelerate the speed response and cause vibrations, which is not what is expected. This paper proposes a way to suppress vibrations by detecting the vibration frequency and extracting the vibration signal as a compensation to the speed feedback. Additionally, in order to improve its disturbance rejection ability, a low-order disturbance observer is proposed. This paper also explains the operation principle of the proposed method by analyzing the transfer function and it describes the design of the controller parameters in detail. Simulation and experimental results are provided to verify the merits of the proposed method. These results also show the good performance of the proposed method. It has a rapid response and suppresses vibrations.

본 논문은 광대역 특성의 뱅뱅 디지털 위상 동기 루프를 설계함에 있어 최적의 루프 이득 선정을 통한 실용적인 선형화 설계 기법을 제안한다. 기존의 이론적 파라미터 설계 기법을 광대역 클럭 발생기 회로에 적용함에 있어 한계점을 설명하고 실제 구현된 뱅뱅 디지털 위상 동기 루프 설계에 대해서 살펴보았다. 본 논문에서는 정수 어레이와 디더 이득은 크게 하되 비례 이득을 작게 설정하여 뱅뱅 디지털 위상 동기 루프의 리미티드 사이클 노이즈를 제거하였다. 제안된 설계 기법을 적용한 뱅뱅 디지털 위상 동기 루프는 기존의 구조에 비교하여 초소형, 저전력, 선형 특성 및 루프 대역폭 조절이 가능한 장점을 보이며, 성능의 우수성을 시뮬레이션을 통하여 검증하였다.

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

This paper deals with the NREL(National Renewable Energy Laboratory) 5 MW reference wind turbine for offshore system. The controller which include MPPT(Maximum Power Point Tracking) control to recover the maximum energy from wind and pitch control to limit the power output is applied to wind turbine. Conventional pitch loops have used the same sensitivity scheduling to the P gain signal and I gain signal(CPS, Collective Pitch gain Scheduling). However, this technique only focuses on power control without considering the load on the wind turbine. In addition, the stability of the system can not be guaranteed since the pitch control loop has a low phase margin. Therefore, this paper proposes a technique, which applies gain scheduling individually to the P gain signal and the I gain signal(IPS, Individual Pitch gain Scheduling) for load reduction. To verify the effect, electrical power and tower root moment DEL(Damage Equivalent Load) were set as performance indices. Simulations were performed for 600 seconds under the wind conditions of the normal turbulence model, the turbulence intensity of16 % and the wind speeds of 12~25 m/s. . The proposed IPS technique was found to reduce the fore-aft moment DEL of the tower up to 14.49 % than the existing collective pitch scheduling.