Earticle

초록

영어

This paper presents a fractional gain-control technique for a digitally controlled oscillator (DCO). The proposed fine-fractional gain-control scheme improves the jitter performance by suppressing the nonlinear effect of a bang-bang digital phase-locked loop (BB-DPLL). In addition, the proposed structure significantly reduces the chip area, because the proposed fractional DCO dithering circuit requires only one accumulator with an N-2-bit width, while conventional topologies require multiple accumulators with N-bit widths. The simulation result shows that the period jitter of the proposed structure (0.83 ps) is three times better than that of a digital PLL based on a conventional second-order sigma-delta modulator (2.58 ps).

목차

Abstract
 1. Introduction
 2. Conventional DCO Dithering for a Fractional Gain Control
 3. Operation Principle and Implementation
 4. Conclusion
 References

키워드

저자

• Kang-Un Choi [ School of Electrical Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju, 28644, Republic of Korea ]
• Jong-Phil Hong [ School of Electrical Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju, 28644, Republic of Korea ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Control and Automation

• 간기

  월간

• pISSN

  2005-4297

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605