Earticle

자신이 쓴 문장과 유사한 문장을 살펴보는 것은 초등 글쓰기 교육을 위한 효과적인 방법 중 하나이지만, 매번 글을 쓸 때마다 교사의 지도가 필요하기 때문에 현실적으로 활용하기 쉽지 않다. 본 논문에서는 이 한계를 극복 하기 위해 컴퓨터가 자동으로 자신이 쓴 문장과 유사한 문장을 실시간으로 선별해 주는 방법을 제안한다. 이 방 법은 단어의 구성 성분을 쪼개는 단계, 쪼갠 단어를 입력으로 활용하여 인코더-디코더 모델을 학습하는 단계, 모델을 통해 얻어낸 추상화된 문장을 활용해 검색하는 단계로 구성된다. 실험 결과, 작은 규모의 데이터에 대해 75%의 정확도를 보임으로써 실용화 가능성이 높은 것으로 나타났다. 이 방법을 통해 학생들은 자신의 어색한 문장을 교정하거나 새로운 표현을 익히고 싶은 경우 다른 사람이 작성한 좋은 예문을 쉽게 참조할 수 있어 자신 의 글쓰기 능력을 향상시키는 데에 큰 도움이 될 것으로 기대된다.

When elementary students write their own sentences, it is often educationally beneficial to compare them with other people’s similar sentences. However, it is impractical for use in most classrooms, because it is burdensome for teachers to look up all of the sentences written by students. To cope with this problem, we propose a novel approach for automatic selection of similar sentences based on a three-step process: 1) extracting the subword units from the word-level sentences, 2) training the model with the encoder-decoder architecture, and 3) using the approximate k-nearest neighbor search algorithm to find the similar sentences. Experimental results show that the proposed approach achieves the accuracy of 75% for our test data.

Low Density Parity Check codes are FEC codes and consequently data rate is more. They are linear error correcting codes for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance, Low Decoding Complexity. The main advantage of the parity check matrix is the decoder can correct all single-bit errors. In this Paper LDPC encoder and decoder architecture for coding 3-bit message vector will be analyzed and also designed using VHDL.

In this paper, we propose an area-efficient architecture of a reed-solomon (RS) decoder/encoder for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circit size and decoding latency has the following two features. First, area-efficeincy has been significantly improved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, modified euclid's algorithms has been implemented by using a new architecture. Experimental results have showed that the decoder/encoder designed by using the proposed method has been implemented with 25% smaller sie over straight forware implementation based on the conventional method [1] and the decoding latency has been reduced.