Earticle

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

A 1.9-GHz linear CMOS power amplifier is presented. An adaptive bias circuit (ABC) that utilizes an AC ground to detect the power level of the input signal is proposed to enhance the linearity and efficiency of the power amplifier. The ABC utilizes the second harmonic component as the input to mitigate the distortion of the fundamental signal. The input power level of the ABC was detected at the AC ground located at the V_DD node of the power amplifier. The output of the ABC was fed into the inputs of the power stage. The input signal distortion was mitigated by detecting the input power level at the AC ground. The power amplifier was designed using a 180 nm RFCMOS process to evaluate the feasibility of the application of the proposed ABC in the power amplifier. The measured output power and power-added efficiency were improved by 1.7 dB and 2.9%, respectively.

CMOS 카메라 영상의 화질을 좌우하는 것은 여러 가지가 있는데 그 중에서 영상 노출시간은 중요한 요소이다. 영상 노출시간이 길게 되면 화면 전체 영상이 밝아지게 되고 노출시간이 짧아지면 전체 영상이 어두워지게 된다. 정지 피사체를 사진 촬영할 경우 자동노출 시스템이 적절한 노출시간을 얻는데 충분한 시간이 주어지기 때문에 실시간성이 요구되지 않는다. 하지만 주행 중인 자동차의 블랙박스 같이 주변 빛 환경이 빠르게 변하게 되면 이에 맞추어서 노출시간도 실시간으로 반응하여 적용되어야 한다. 이를 위해서는 실시간성과 주변 빛 환경에 대하여 강건한 자동노출 시스템이 요구된다. 본 논문에서는 ZYNQ의 로직과 ARM코어를 적용한 임베디드 시스템 설계로 병렬 연산처리 가능한 실시간 제어 시스템을 설계하였고 이를 바탕으로 PID 제어를 통해서 66ms 이내에 원하는 목표 값으로 수렴하고 노이즈에 강건한 실시간 CMOS 자동 노출 시스템을 개발하였다.

There are many factors that influence the image quality of CMOS camera images, among which the image exposure time is an important factor. If the image exposure time is long, the entire image on the screen becomes brighter. If the exposure time is shorter, the entire image becomes darker. When photographing a still image, real time is not required because the automatic exposure system is given sufficient time to obtain an appropriate exposure time. However, if the surroundings and environment change rapidly like the black box of a driving car, the exposure time should be applied in response to real time. To this end, a robust automatic exposure system for real-time performance and ambient light environment is required. An automatic exposure system that has real-time capability and is robust against the ambient light environment is required. we designed a real-time control sysem capable of parallel operation processing through the design of an embedded system using zynq's logic and ARM core, and developed a real-time CMOS automatic exposure system that is robust to noise and converges to a desired target value within 66 ms through PID control.

이 논문에서는 고속 저전력 분야에 적용하기 위한 8비트, 15MHz A/D 변환기 설계 에 관해 기술한다. 2단 플래시 방식인 서브레인징 구조 A/D 변환기에서 칩 면적을 줄 이기 위해 저항의 수를 감소시킨 전압분할 회로를 설계하였다. 비교기는 80 dB의 이득, 50 MHz의 대역폭, 오프셋 전압이 0.5mV이고, 전압분할 회로의 최대오차는 1mV이다. 설계된 A/D변환기는 ＋5/-5V 공급 전압에 대해 전력소비가 150mW, 지연시간이 65ns 이다. A/D 변환기는 N-well공정을 이용하여 설계하고, 제작하였다. 제안된 변환기는 고속, 저전력, 소형 단일 칩 아날로그-디지탈 혼합 시스템 응용에 적합하다. 시뮬레이 션은 PSPICE를 이용하여 수행하였고, 1차 가공된 칩을 데스트 하였다.

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

본 논문은 지그비(ZigBee) 응용을 위한 2.4 GHz CMOS RF 프론트-엔드(front-end) 설계에 관한 기술이다. Front-End는 저잡음 증폭기(LNA), 주파수 변환기(Mixer)로 구성 되며, 2 MHz의 중간 주파수 (IF : intermediate frequency)를 사용 한다. LNA는 피드백저항을 사용한 Common-Source(CS with resistive feedback) 구조와 축퇴(degeneration) 인덕터를 사용 하였고, 20db의 전압 이득을 디지털신호로 조절할 수 있다. Mixer는 저전류 소모를 고려하여 수동(passive) 구조로 설계하였다. RF front-end는 $0.18{\mu}m$ 1P6M CMOS 공정을 이용하여 구현하였으며 1.8V의 전압으로부터 3.28 mA의 전류 소모를 하며 측정 결과 NF는 4.44 dB, IIP3는 -6.5 dBm을 만족시킨다.

A 2.4 GHz CMOS RF front-end using for ZigBee application is described The front-end consists of a low noise amplifier and a down-mixer and uses a 2 MHz IF frequency. A common source with resistive feedback and an inductive degeneration are adopted for a low noise amplifier, and a 20 dB gain control step is digitally controlled. A passive mixer for low current consumption is employed. The RF front-end is implemented in 0.18 ${\mu}m$IP6M CMOS process. The measured performance is 4.44 dB NF and -6.5 dBm IIP3 while consuming 3.28 mA current from a 1.8 V supply.

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

본 논문에서는 캐리 선택 방식과 캐리 우회 방식에 의거한 비동기 가산기의 설계에 대하여 기술한다. 이러한 기법을 사용함으로써 본 논문의 가산기는 기존의 리플 캐리 방식의 가산기에 비하여 보다 빠른 속도로 동작한다. 본 논문에서는 CMOS 도미노 논리를 사용하여 가산기를 설계하였으며 비동기 가산기의 동작 완료를 감지할 수 있는 회로를 트리 형태로 구현함으로써 동작 완료에 소요되는 시간을 줄일 수 있도록 하였다. 실험 결과에 의하면 제안된 가산기들은 평균적으로 리플 캐리 방식에 비하여 50 퍼센트 이상의 속도 개선을 기대할 수 있음을 알 수 있다.

This paper describes the design of asynchronous adders based on carry selection and carry bypass techniques. The designs are faster than existing asynchronous adders which are based on ripple carry technique. It is caused by reducing the carry transfer time by using carry selection and carry bypass techniques. Also, the design uses tree structure to reduce the completion sensing time. The proposed adders are designed with CMOS domino logic and experimented with HSPICE simulator. Experimental results show that the proposed adders can be faster about 50% in average cases than previous ripple carry adders.

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

본 논문은 1P8M CMOS $0.13{\mu}m$ 공정을 이용하여 GPS응용에 적합한 프론트-엔드(front-end)를 구현하였다. 저잡음 증폭기(LNA)는 능동 안테나와 수동 안테나를 지원하기 위해 높은 전압이득과 낮은 잡음지수(Noise Figure)의 LNA1모드와 낮은 이득과 높은 입력 3차 교차점(IIP3: 3rd Input Intercept Point)의 LNA2모드로 동작한다. 두 LNA의 측정된 성능은 1.2 V의 공급전압에서 각각 3.2/2 mA의 전류를 이용하여 16.4/13.8 dB 이득과, 1.4/1.68 dB NF, 그리고 -8/-4.4 dBm의 IIP3값을 갖는다. 쿼드 하향주파수 혼합기(quadrature downconversion 혼합기)는 트랜스임피던스 증폭기(transimpedance amplifier)와 가변저항을 이용하여 27.5 dB에서 41 dB의 변환이득을 갖는다. 프론트-엔드는 LNA1모드 동작 시 6.6 mW의 전력을 소모하여 39.8 dB의 변환이득, 2.2 dB의 잡음지수와 -33.4 dBm의 IIP3의 성능을 갖는다.

The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.

The paper describes variable circuits technique the enable of differential circuit of charge pump. It is able to pump an input voltage of 2V to measure several output voltage through several clock signal with each pumping capacitor of 1 pF and smoothing capacitor of 1 pF at the output. From the simulation result, it is evident that charge pump circuits offer verity high voltage pumping gain. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

The paper describes variable circuits technique the enable of differential circuit of charge pump. It is able to pump an input voltage of 2V to measure several output voltage through several clock signal with each pumping capacitor of 1 pF and smoothing capacitor of 1 pF at the output. From the simulation result, it is evident that charge pump circuits offer verity high voltage pumping gain. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

This paper presents the design and analysis of 2.45GHz Low-IF Mixer using CMOS 0.18um. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique, and the resonating technique for the tail capacitance. And the design of this Double Balance Mixer is based on its lineaity since it is important in the interference cancellation system. The low flicker noise mixer is implemented by incorporating a double balanced Gilber-type configuration, the RF leakage-less current bleeding technique, and Cp resonating technique. The proposed mixer has a simulated conversion gain of 16dB a simulated IIP3 of -3.3dBm and P1dB is -19dBm. A simulated noise figure of 6.9dB at 10MHz and a flicker corner frequency of 510kHz while consuming only 10.65mW od DC power. The layout of Mixer for one-chip design in a 0.18-um TSMC process has 0.474mm x 0.39 mm size.

Recently, the high speed device to device(D2D) wireless communication technology has been studied for short distant mobile data transfer application. This paper presents 60 GHz OOK(On-Off Keying) non-coherent receiver which is a strong candidate for high speed D2D communication technology. The OOK receiver architecture is used because of its simple structure and low power characteristic. The receiver consists of three-stage low noise amplifier (LNA), fully differential envelop detector, and limiting amplifier(LA). The measured receiver shows 54 dB peak gain at -55 dBm input power level. The sensitivity of the receiver is measured -50 dBm under 3 Gbps data rate. The proposed receiver is fabricated with 65 nm CMOS process and its measured power consumption is only 21.5 mW. As a result, the proposed receiver achieves energy efficiency of 7.12 pJ/bit.