년 - 년
Class-AB CMOS Buffer with Low Power and Low Leakage Using Transistor Gating Technique
보안공학연구지원센터(IJAST) International Journal of Advanced Science and Technology Vol.58 2013.09 pp.1-12
※ 원문제공기관과의 협약기간이 종료되어 열람이 제한될 수 있습니다.
A rail-to-rail class-AB CMOS buffer amplifier is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.05%), low leakage and reduced area (2.8%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with Cadence software. This analog circuit is performed with reduced performance degradation as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay range i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by 30% (in ns) at 3V square wave input. The measured quiescent current is 56μA.
2.45GHz CMOS Up-conversion Mixer & LO Buffer Design
[Kisti 연계] 대한전자공학회 Journal of semiconductor technology and science Vol.2 No.1 2002 pp.30-40
※ 협약을 통해 무료로 제공되는 자료로, 원문이용 방식은 연계기관의 정책을 따르고 있습니다.
A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.
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