Earticle

초록

영어

A rail-to-rail class-AB CMOS buffer amplifier is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.05%), low leakage and reduced area (2.8%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with Cadence software. This analog circuit is performed with reduced performance degradation as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay range i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by 30% (in ns) at 3V square wave input. The measured quiescent current is 56μA.

목차

Abstract
 1. Introduction
 2. Class-AB Rail-to-Rail Buffer
  2.1. Rail-to-rail Input Swing
  2.2. Class-AB Buffer
  2.3. Power Consumption of Circuit
  2.4. Analysis of Settling Time and Slew Rate
 3. Low Power Dissipation Scheme for CMOS Buffer
 4. New High Speed Buffer with Low Power
 5. Simulation Results
 6. Conclusion
 Acknowledgements
 References

키워드

저자

• Sadhana Sharma [ Research Scholar of ITM University, Gwalior, India ]
• Shyam Akashe [ Associate Professor, Dept. of ECE, ITM University, Gwalior, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605