Earticle

With the recent development of diagnosis using radiation and increasing demand of the medical treatment, we need to minimize radiation exposure dose. So, This is the method which reduce patient dose by measuring surface dose of radiographic change factor and by comparing theoretical and actual dose, when we take an X-ray which is generally used. By changing the factor of kV, mAs, FSD, whose range is 60 to 120 kV, 20 to 100 mAs, 80 to 180 cm, we compared theoretical surface dose with actual surface dose calculated by the simple calculation program, Bit system, and NDD-M method As a result, when kV and mAs were higher, theoretical surface dose and actual surface dose were more increased. but the higher FSD was, the more decreased surface dose was. According to this, the error were measured about 0.1 to 0.2 mGy in low dose part and about 0.7 to 1.5 mGy in high dose part. Therefore, this shows that theoretical surface dose calculation method is more correct in low dose part than in high dose part. In conclusion, we will have to make constant efforts which can reduce patient and radiographer’s exposure dose, studying methods which can predict patient’s radiation exposure dose more exactly.

이 연구는 대한민국 해군에 배치된 함정 엔진의 현 실태를 종합적으로 분석하고 함정 엔진의 MRO(Maintenance ·Repair·Operation) 및 엔진 운영 효율성 향상, 서비스 수명 연장, 유지보수 비용 절감을 위한 자동화 시스템을 제안한다. 함정의 주 엔진 종류인 가스터빈 및 디젤 엔진 플랫폼으로는 국산화율이 현재 미흡한 실정이다. 국산화 및 부담되는 지속 적인 엔진 유지 보수의 한계점을 최소화하고자 이 연구는 디지털 트윈(Digital Twin Model) 모델 기반 머신러닝(ML) 기반 예측 유지보수, 센서 네트워크 내장형 테스트(BIT) 프로그램을 활용한 통합 엔진 관리 시스템을 제안한다. 센서 네트 워크 설계로 실시간 고장 탐지, ML 기반 잔여 사용 수명(RUL) 추정 등을 통해 엔진 운영 유지시킨다. 또한 하드웨어-인- 더-루프(HIL) 검증 등을 포함한 단계별 구현 로드맵을 통해 가상 모델과의 오차율 최소화된 실시간 유지할 수 있다. 이러 한 시스템 제안을 통해 수명 주기 관리의 상당한 개선, 선박 유지 보수 절감 및 추후 독자적 선박 엔진 개발의 전략적 자율성 강화를 목표로 한다.

This study comprehensively analyzes the current status of ship engines deployed in the Republic of Korea Navy and proposes an automated system to improve ship engine MRO(Maintenance·Repair ·Operation), engine operational efficiency, extend service life, and reduce maintenance costs. The domestic production rate of gas turbine and diesel engine platforms, which are the main types of ship engines, is currently insufficient. To overcome this and reduce maintenance burdens, an integrated engine management system is proposed. It uses digital twin technology and machine learning (ML)-based predictive maintenance through a built-in test (BIT) program embedded in a sensor network. Through sensor network design, real-time fault detection, and ML-based remaining useful life (RUL) estimation, the system ensures engine operational maintenance. Additionally, through a phased implementation roadmap including hardware-in-the-loop (HIL) verification, real-time maintenance with minimized error rates compared to virtual models is achievable. This approach aims to improve lifecycle management, lower ship maintenance costs, and support independent development of future naval propulsion systems.

This study aims to implement an integrated control system for a micro drill bit grinding machine to increase the processing stability and production efficiency of the equipment. The system consists of a WTGM mechanism, an environmental measurement sensor (RMU device), a control server, and a control client, and collects production statistics and alarm information in real time to enable central monitoring and statistical analysis. Through the control system, managers can check data and solve problems anytime and anywhere, thereby increasing the stability and efficiency of the production process. As a result of the experiment, it showed excellent performance in all evaluation items such as alarm occurrence time, notification time, and event operation time through temperature and humidity sensors, and contributed to productivity improvement through immediate response through e-mail and SNS notification. In conclusion, the implemented system optimizes the operating rate and inventory management of the equipment through real-time monitoring and yield analysis, and it is expected to improve system performance as it can be used as learning material for pattern analysis and deep learning algorithms in the future.

Since OFDM system suffers from high peak-to average power ratio(PAPR) drawbacks, more energy has been converted to seek for a new substitutable system which can maintain OFDM system’s inherent virtues while avoid its defects. Consequently, a new multicarrier system called as CI/OFDM system has been proposed which applied carrier interferometry(CI) code to OFDM system. Due to its low PAPR advantage and orthogonal property, it has received more and more attention. Simultaneously, an old technique called single carrier(SC) system has retaken its attractions for the same purposes. This paper analyzes two cyclic prefixed transmission schemes variants of OFDM system: 1.carrier interferometry-Orthogonal Frequency-Division Multiplexing (CI/OFDM); 2. Cyclic prefixed single carrie(CP-SC) with frequency domain equalization. We compare the achievable bit rate transmission of the two systems in terms of signal to noise ratio(SNR) by mathematical derivation. We demonstrated that CI/OFDM achieves a bit higher transmission bit rate to that of the CP-SC with frequency domain equalizer.

Optical code division multiple access system (OCDMA) has been important with increasing demands of high capacity and speed for communication in optical networks. Due to OCDMA technique high efficiency is achieved, hence fiber bandwidth is fully used. In this paper we will focus on different codes i.e MD (Multi Diagonal) FCC (Flexible cross correlation), DCS (Dynamic cyclic shift) code with BER parameter. Due to this codes we will eliminated MAI (multiple access interference) and improve BER (bit error rate), PIIN (Phase induced intensity noise) and make orthogonality between users in the system .We will use AND subtraction detection technique to implement these codes with technique of OCDMA using optiwave system design tool.

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phasedarray antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 μm RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm2. In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 ‒ 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

The environment development for deep sleep has been studied using analysis results of the big data about vital signs and parameters in the bedroom. The organic light emitting diode (OLED) illuminations of the bedroom are dimming using analysis results of the big data. Therefore, a low-power and compact design of dimming part is required for OLED illumination system. In this paper, the optimized control block of the clock cut-off circuit was designed using De Morgan’s laws with adiabatic dynamic CMOS logic (ADCL) digital 3-bit pulse width modulation (PWM). The designed clock cut-off circuit pauses the D-flipflops (D-ffs) after cutting off the clock at both 0 % and 100 % pulse width of PWM output for dimming. As a result, 10 transistors of the miniaturized control block were reduced and layout area of the optimized control block is 2,198.0μm2 using Rohm 0.18μm standard CMOS model .The operation of control block of clock cut-off circuit with ADCL 3-bit digital PWM is confirmed by post-simulation of hspice.

This paper has proposed a serial 8-bit DAC for column driver circuits of mobile displays using LTPS TFTs. The DAC circuit takes very small area by using parasitic capacitance of column lines as sampling and holding capacitors. Moreover, the proposed DAC does not need the analog buffer, because the DAC operation is performed on the column lines. For the data driver circuits of 2-inch qVGA OLED panel, the DAC area is $84um{\times}800um$ and the simulated DAC power consumption is 8.5mW with 10-V supply voltage.

전리방사선을 이용한 의료진단검사는 장치의 발전과 더불어 환자의 삶을 개선시키고 의료검사의 혁명을 가지고 왔다. 하지만 이러한 의료영상의 발전은 대중에 의한 전리방사선피폭의 증가의 원인이 되었다. 이러한 가운데 ICRP에서는 각 국가 및 지역의 실정에 맞게 진단참고준위를 사용하도록 권고하고 있으며, 우리나라에서도 2007년 식품의약품안전청에서 환자선량측정 가이드라인을 제시하였다. 하지만 임상에서는 대부분 선량계가 없어 X선 검사시 환자피부선량을 알 수가 없는 것이 현실이다. 이에 저자는 bit system을 이용하여, PC상에서 엑셀프로그램을 이용하여 간단하게 환자선량을 알 수 있게 프로그램화 하여 그 유용성을 검토하였으며, 그 결과 실측값과 계산값은 약 10% 정도의 차이로 우수한 결과를 나타내었다.

The medical diagnostic examination using ionizing radiation has improved the patients' life and brought revolution in medical examination along with the mechanical development. However, the development of medical imaging systems has also been the reason to increase the patients' exposure for ionizing radiation. ICRP recommends that each country adopts diagnostic reference levels depending on regional and national situations. The Korea Food & Drug Administration suggested the dosimetry measurement guideline for patients in 2007. Nonetheless, in reality, it is hard to know the skin dose of the patients when applying a x-ray since there is no radiation dosimeter in most of clinical situation. Therefore, this study sets a program based on the bit system to figure out easily the skin dose of a patients using MS Excel program in the PC setting. The results showed 10% better outcome.

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

MPEG-4 FGS is one of scalable video coding schemes specified In ISO/IEC 14496-2 Amendment 2, and particularly standardized as a scheme for providing fine granular quality and temporal scalabilities. In this paper, we propose a sign-bit reduction technique in embedded bit-plane coding to enhance the coding efficiency of MPEG-4 FGS system. The general structure of the FGS system for the proposed scheme is based on the standard MPEG-4 FGS system. The proposed FGS enhancement-layer encoder takes as input the difference between the original DCT coefficient and the decision level of the quantizer instead of the difference between the original DCT coefficient and its reconstruction level. By this approach, the sign information of the enhancement-layer DCT coefficients can be the same as that of the base-layer ones at the same frequency index in DCT domain. Thus, overhead bits required for coding a lot of sign information of the enhancement-layer DCT coefficients in embedded bit-plane coding can be removed from the generated bitstream. It is shown by simulations that the proposed FGS coding system provides better coding performance, compared to the MPEG-4 FGS system in terms of compression efficiency.

본 논문은 YOLO V3 알고리즘을 기반으로 한 드릴비트 이물질 검사 시스템을 구현하고 그 성능을 평가하였다. 연구는 드릴비트의 정상 상태와 이물 상태를 구분하기 위해 600장의 학습 데이터를 사용하여 YOLO V3 모델을 학습시켰다. 구현된 검사 시스템은 자동검사를 통해 드릴비트의 상태를 정확히 분석하고 결함을 효과적으로 탐지하였다. 성능 평가는 2000회 이상 사용된 드릴비트를 대상으로 수행되었으며, 재연마 가능 여부를 판별하는 인식률 98%를 달성하였다. 세척 공정에서 이물질 제거의 목표를 99.6%로 평가하였으며, 자동 검사 시스템은 시간당 500개 이상의 드릴비트를 검사할 수 있어 기존 수동 검사 방법에 비해 약 4.3배 더 빠르고 99%의 높은 정확도를 기록하였다. 이러한 결과는 자동화된 검사 시스템이 검사 속도와 정확성을 획기적으로 개선할 수 있음을 보여주며, 제조현장에서의 품질 향상과 비용 절감에 기여할 수 있음을 알수있다. 향후 연구에서는 시스템 최적화와 성능 향상을 통해 더욱 효율적이고 신뢰성 높은 검사 기술 개발이 필요하다.

This paper implemented a drill bit foreign matter inspection system based on the YOLO V3 algorithm and evaluated its performance. The study trained the YOLO V3 model using 600 training data to distinguish between the normal and foreign matter states of the drill bit. The implemented inspection system accurately analyzed the state of the drill bit and effectively detected defects through automatic inspection. The performance evaluation was performed on drill bits used more than 2,000 times, and achieved a recognition rate of 98% for determining whether resharpening was possible. The goal of foreign matter removal in the cleaning process was evaluated as 99.6%, and the automatic inspection system could inspect more than 500 drill bits per hour, which was about 4.3 times faster than the existing manual inspection method and recorded a high accuracy of 99%. These results show that the automated inspection system can dramatically improve inspection speed and accuracy, and can contribute to quality improvement and cost reduction in manufacturing sites. In future studies, it is necessary to develop more efficient and reliable inspection technology through system optimization and performance improvement.

본 논문에서는 PCM/FM시스템에 대한 비트(bit)오차 확률식을 구하여 이를 수치적으로 계산하여 검토를 행했다. 변조전 필터를 거친 NRZ-L 이진 펄스예을 변조 신호로 하여 반송파를 주파수 변조하였고, 리미터와 변별기를 검출기로 이용하였다. RF 스펙트럼의 제한과 비트 오차 확률의 감소면에서 볼 때, 주파수 편이화 h를 3WT가 되도록 설계하는 것이 적당함을 알 수 있었다. 여기서 W는 변조전 필터의 대역폭이고 T는 한 비트당 시간 간폭이다.

The bit error probability of PCM/FM system was derived and numerically calculated. Binary NRZ-L baseband signal was premodulation filtered to frequency modulate a sinusoidal carrier, and a common circuit of limiter-discriminator was employed as a detector. Considering both RF spectrum limitation and bit error Probability reduction, it was found that h ≒ 3WT would be reasonable, where h is the frequency deviation ratio, W is the bandwidth of a premodulation filter and T is the time interval of one bit.

The operation of a first-order 2-bit adaptive sigma-delta modulation system is described and discussed in this paper. The system operation is based on the combination of both "memory" and "look-ahead" estimation in the employed step-size adaptation algorithm of the basic quantizer. In comparison to simple systems and other adaptive sigma-delta systems, computer simulation results show that these features of the described system are responsible for the high SNR values and the extended dynamic range achieved for AC signals as well as the noise power reduction of almost 10 dB and the complete elimination of the idle tones for DC signals. However, such an advantageous performance requires the least possible multiplicative error accumulation, and this cannot be achieved without analog circuits of the highest possible accuracy.

The expandable 4 bit adder<SUB>tracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$<</SUB> CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

In this paper, an adaptive minimum transmit power modulation scheme under constant data rate and fixed bit error rate (BER) for the multiple-input multiple-output (MIMO) system is proposed. It adjusts the modulation order and allocates the transmit power to each spatial sub-channel when meeting the user's requirements at the cost of minimum transmission power. Compared to the other algorithm, it can obtain good performance with lower computational complexity and can be applied to the wireless communication system. Computer simulation results present the efficiency of the proposed scheme. And its performance under different channel condition has been compared with the other algorithm.