Earticle

초록

영어

The environment development for deep sleep has been studied using analysis results of the big data about vital signs and parameters in the bedroom. The organic light emitting diode (OLED) illuminations of the bedroom are dimming using analysis results of the big data. Therefore, a low-power and compact design of dimming part is required for OLED illumination system. In this paper, the optimized control block of the clock cut-off circuit was designed using De Morgan’s laws with adiabatic dynamic CMOS logic (ADCL) digital 3-bit pulse width modulation (PWM). The designed clock cut-off circuit pauses the D-flipflops (D-ffs) after cutting off the clock at both 0 % and 100 % pulse width of PWM output for dimming. As a result, 10 transistors of the miniaturized control block were reduced and layout area of the optimized control block is 2,198.0μm2 using Rohm 0.18μm standard CMOS model .The operation of control block of clock cut-off circuit with ADCL 3-bit digital PWM is confirmed by post-simulation of hspice.

목차

Abstract
 1. Introduction
 2. Adiabatic Logic
  2.1. Adiabatic Charging
  2.2. Adiabatic Dynamic CMOS Logic (ADCL)
 3. Optimization of Control Block of Clock Cut-off Circuit
 4. Simulation Results
 5. Conclusion
 Acknowledgments
 References

키워드

저자

• Seung-Il Cho [ Innovation Center for Organic Electronics, Yamagata University ]
• Sung-Dae Yeo [ Graduate School of NID Fusion Technology, Seoul National University of Science &Technology ]
• Seong-Kweon Kim [ Graduate School of NID Fusion Technology, Seoul National University of Science &Technology ]
• Michio Yokoyama [ Graduate School of Science and Engineering, Yamagata University ] Corresponding author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Smart Home

• 간기

  격월간

• pISSN

  1975-4094

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605