Earticle

Image hiding is a technique that embeds the images into a cover image which makes the watermarks imperceptible so that they can be securely transmitted to the receiver. In this paper, an effective color image watermarking method based on the marginal strategy is proposed. The method uses logical operators like AND and XOR on the nibble to hide the image with in the cover image. To test the robustness of the stego image the present method is applied on different kinds of cover images and the resulting perceptual quality is good.

In this paper we have designed a fair e-cash system using Schnorr’s one-time signature and Okamoto-Schnoor blind signature. In addition, the proposed e-cash system is constructed using elliptic curve cryptosystems (ECC) under the limited-storage environment for mobile devices such as smart cards, PDA etc able to efficiently store the coin streams. Furthermore, this system prevents criminal’s activities by means of the two common cryptographic techniques double-spending detection and fair tracing.

In this paper we have proposed an efficient password security of Three- Party Key Exchange Protocol based on Elliptic Curve Discrete Logarithm Problem. Key exchange protocols allow two parties communicating over a public network to establish a common secret key called session key. Due to their significance by in building a secure communication channel, a number of key exchange protocols have been suggested over the years for a variety of settings. Here we have taken two one-way hash functions to build the level of security high.

The idea of using multivariate polynomials as public keys has attracted several cryptographers, SFlash signature scheme is a variant of the Matsumoto and Imai multivariate public Key cryptosystem and selected by NESSIE Consortium. In this paper we describe a hardware implementation of SFlash based on bit-parallel architectures to achieve high speed circuits for operations on Finite Fields which can be efficiently used as an authentication unit in wireless devices, smart cards and RFID networks. We have proposed a new generalization to Karatsuba-Ofman multiplier as the core of the design. An ASIC chip can be realized with 78K gates counts and 2.8 mm2 die size with 0.35 mm CMOS technology, with a maximum clock frequency 140 MHZ, which takes about 21.5 ms to sign 259-Bits data.