Earticle

FMCW 레이더에서 주파수 램프 신호를 발생시키기 위하여 필요한 타입-3 PLL의 설계 가이드를 제시하였다. 그러기 위해서 개루프 전달함수의 크로스오버 주파수를 1 Hz로 정규화 한 조건에서 Pspice 시뮬레이션을 통하여 폐루프 특성을 비교하였다. 결론적으로 타입-3 PLL의 1) 위상여유는 45도로 하고, 2) 두 개의 영점은 같도록 하며, 3) PLL 차수를 높이기 위한 극점은 개루프 전달함수의 크로스오버 주파수보다 10배 정도 크게 할 것을 권한다.

A design guide to type-3 PLLs for FMCW radars is provided. To do that, the cross-over frequencies of the open-loop transfer functions were normalized to 1 Hz and closed-loop properties were compared through simulations using Pspice. As a result, several guides to design type-3 PLLs were provided: 1) secure 45 degrees of phase margin, 2) locate two zeroes at an identical frequency, and 3) poles may be added to raise order of the PLL at higher frequencies than the cross-over frequency of the open-loop transfer function about ten times.

Deep learning plays a major role in the present video processing tools and algorithms. To? alleviate the limitations of present in-loop filters in the scalable extension of HEVC (SHVC), a combined residual network (CResNet) in-loop filtering is proposed in this paper. The proposed CResNet in-loop filter exploits layer information available in the spatial temporal domain to restrain the visual artifacts like blocking and ringing. Particularly, the block information related to current and co-located blocks of the spatial and temporal base layer reference frames are considered to optimize the in-loop filtering. The proposed architecture has four convolution layers at the base layer and two convolution layers at the enhancement layer that significantly reduces the coding complexity and memory. Additionally to completely train the input content and also to enhance the in-loop filter performance, the on/off level control flag for coding tree Unit (CTU) is sensed using rate distortion optimization (RDO) approach. The experimental results demonstrate that the proposed architecture provides up to 6.2% to 7.2% reduction in bit rate and 1.01 dB improvement in PSNR compared to the standard SHVC codec.

위성 기반 측위 시스템은 위치 기반 기술의 핵심 기술로서, CDMA 시스템을 사용한다. CDMA 시스템에서 원활한 위치 측위를 하기 위해서는 확산 부호의 정확한 동기가 이루어져야 한다. 본 논문은 확산 부호의 동기 기법 가운데 부호 추적 기법에 초점을 맞춘다. 특히 다중 경로 환경에서 기존의 부호 추적 기법인 DLL 방법은 적합하지 않다. 본 논문은 수신 신호에서 다중 경로 신호를 축출하여 이를 부호 추적 기법에 사용하는 방법을 제안한다. Spirent simulator를 이용하여 제안 기법을 검증하고 성능 평가를 보인다.

The navigation system like GPS which is core technology is based on Code Division Multiple Access(CDMA) techniques. To receive satellite signal smoothly in CDMA, received signals have to synchronize with spread code. In this paper, we focus on the code tracking methods among synchronization techniques. The conventional delay lock loop(DLL) is unsuitable for multi-path channel. We will introduce how it overcomes distortion by multi-path. We will propose method that separates out multi-path signals and tracks the each path signals. And we will confirm performance of proposed method using Spirent simulator.

This paper presents the LQ-Servo control with observer for TCP/AQM system considering an input time-delay. This controller structure is made by taking a traditional servo mechanism based on Linear Quadratic approach and by augmenting a new state variable to the feed forward loop. In order to estimate the state of TCP window packet size, the control structure is extended with observer based on Kalman filter.

This paper proposes an efficient full-duplex multiple input multiple output (MIMO) relay in wireless multihop networks. The proposed relay consists of a minimum mean square error (MMSE) filter, a decode-and-forward protocol processor, and a modified Alamouti encoder. In consideration of the tradeoff between performance and complexity, the MMSE filtering is presented to suppress the spatial loop interference, and the modified Alamouti encoding is simply added to improve the performance of the destination by intimately collaborating with the relay. Simulation results confirm that the proposed method outperforms the conventional methods at the expense of a reasonable increase in complexity.

본 논문에서는 UHD급 영상의 실시간 처리를 위한 고성능 HEVC(High Efficiency Video Coding) In-loop Filter 부호화기의 효율적인 하드웨어 구조를 제안한다. HEVC는 양자화 에러로 발생하는 화질 열화 문제를 해결하기 위해 Deblocking Filter와 SAO(Sample Adaptive Offset)로 구성된 In-loop Filter를 사용한다. 본 논문에서 제안하는 In-loop Filter 부호화기 하드웨어 구조에서 Deblocking Filter와 SAO는 수행시간 단축을 위해 $32{\times}32CTU$를 기준으로 2단 하이브리드 파이브라인 구조를 갖는다. Deblocking Filter는 10단계 파이프라인 구조로 수행되며, 메모리 접근 최소화 및 참조 메모리 구조의 단순화를 위해 효율적인 필터링 순서를 제안한다. 또한 SAO는 화소들의 분류와 SAO 파라미터 적용을 2단계 파이프라인 구조로 구현하고, 화소들의 처리를 간소화 및 수행 사이클 감소를 위해 두 개의 병렬 Three-layered Buffer를 사용한다. 본 논문에서 제안하는 In-loop Filter 부호화기 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 0.13um CMOS 표준 셀 라이브러리를 사용하여 합성한 결과 약 205K개의 게이트로 구현되었다. 또한 110MHz의 동작주파수에서 4K UHD급 해상도인 $3840{\times}2160@30fps$의 실시간 처리가 가능하다.

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 in-loop filter의 하드웨어 구조 설계에 대해 기술한다. in-loop filter는 deblocking filter와 SAO로 구성되며, 블록 단위 영상 압축 및 양자화 등에서 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC는 $64{\times}64$ 블록 크기까지 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 in-loop filter의 deblocking filter 모듈과 SAO 모듈은 최소 연산 단위인 $8{\times}8$ 블록 연산기로 구성하여 하드웨어 면적을 최소화하였다. 또한 SAO에서는 $8{\times}8$ 블록의 연산 결과를 내부레지스터에 저장하는 구조로 $64{\times}64$ 블록 크기를 지원하도록 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 180nm 셀 라이브러리로 합성한 결과 동작 주파수는 270MHz이고, 전체 게이트 수는 48.9k이다.

본 논문에서 5.8GHz의 주파수 대역에서 사용할 수 있는 향상된 커플링 구조와 크기를 줄인 dual-mode microstrip bandpass filter를 설계하였다. 여기서 meander loop resonator를 쓰는 이유는 크기가 작고 방사 손실이 적으며 패턴이 간단하기 때문이다. 또한 이와 비슷한 특성을 갖는 ring, square patch, disk등은 불연속 성분을 가짐으로써 이중모드의 구현이 가능하다. 향상된 형태의 dual-mode microstrip bandpass filter의 변형된 T-shaped meander loop resonator를 소형으로 발전되고. 높은 선택도를 가지는 구조이다. 이 형태의 filter에서 150MHz의 bandwidth을 가지고 5.8GHz주파수를 가지는 구조로 설계하였다.

HEVC(High Efficiency Video Coding)는 현재 표준화가 진행되고 있는 새로운 비디오 부호화 표준의 가칭이다. 이 표준화에서는 H.264/AVC를 넘어선 높은 부호화 성능을 갖기 위해서 다양한 방법들이 논의되고 있으며, 그 중에서 deblocking filter 및 adaptive loop filter 기술에 대해 본 고에서 설명하고자 한다. 기술적으로 deblokcing 필터와 adaptive loop filter는 양자화 및 부호화 연산과 정에서 손실되는 정보를 줄이기 위해 복원된 영상에 필터링을 수행함으로써주관적화질을향상시키기위한기술이다.

In this letter, we present an enhanced block-based adaptive loop filter (E-BALF) with multiple filter symmetric structures. The E-BALF adapts various filter symmetric structures in a rate-distortion optimization sense, reflecting the statistical properties of each image in a video sequence. Experimental results show that the proposed method achieves a reduction in the Bj${\phi}$ntegaard delta (BD)-bitrate by an average of 9.60% compared with Joint Model 11.0 of H.264/AVC. Compared to the state-of-the-art BALF, a reduction of up to 1.13% in BD-bitrate is achieved.

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

A wavelength-selective reflector, composed of a double-ring-resonator add/drop filter and a loop-back mirror at the drop port to be used for a hybrid-integrated tunable laser is designed and fabricated. High-index-contrast polymer waveguide is used to realize a compact device as small as $2mm{\times}0.4mm$. The radii of the rings are slightly different from each other to obtain a wide wavelength tuning via a vernier effect. Peak reflectivity is measured to be 52% for TE mode and polarization-dependent wavelength shift is 0.95 nm. The tuning range is measured to be about 42 nm for applied current as small as 46 mA.

In this study, a novel third-order bandpass filter, which is based on a rectangular closed loop resonator, is presented. By adding a series resonator to the conventional loop resonator, the resonator's even resonant mode is split into two modes, while the odd resonant mode is not affected. Therefore, by varying the values of the series resonator elements, the resonant frequencies of two even modes can be determined independent of the odd-mode resonant frequency. In the proposed triple-mode filter design, instead of using a lumped series resonator, a T-shaped transmission line is coupled to the resonator via a small gap. To verify the design method, a filter is designed at 2.4 GHz with a bandwidth of 100 MHz. The improved performances of the proposed triple-mode filter are compared with those of the conventional dual mode filter.

In this paper, we present a novel design for a dual-band bandpass filter (BPF) based on the conventional second-order, open-loop BPF. By adding series resonant circuits to the open ends of the resonator, we can create two resonant modes from the even and odd modes. One pair of the even and odd modes constitutes the upper passband, while the other pair constitutes the lower passband. By adding another series resonant circuit to the open-loop resonator, we can control the bandwidth of either the upper passband or the lower passband. We can replace the series resonant circuits with simple microstrip line resonators. A dual-band BPF working at both Wi-Fi bands (2.4 GHz and 5.8 GHz bands) is designed based on the proposed method and is tested. The measured and simulated results show excellent agreement.

A self-oscillating class-D audio amplifier adopting the phase-shifting looap filter in the feedback filter is proposed. To validate the design, a mathematical model is proposed. It is alleged in a very simple form which describes the switching frequency variation as the function of the modulation depth to be applied to any general structure: phase shifting, time delay of the loop, and the hysteresis window at the comparator. The main focus is set on the analysis of the phase-shifting filter which shows the least dependency on the modulation depth.

In high dynamic situations, the GPS carrier tracking loop requires a wide bandwidth to track a carrier signal because the Doppler frequency changes more rapidly with time. However, a wide bandwidth allows noises within the bandwidth of the tracking loop to pass through the loop filter. As these noises are used in the numerical controlled oscillator(NCO), the carrier tracking loop of a GPS receiver shows a degraded performance in high dynamic situations. To solve this problem, an adaptive two-stage Kalman filter, which offers the NCO a less noisy phase error, can be used. This filter is based on a carrier phase dynamic model and can adapt to an incomplete dynamic model and a quickly changed Doppler frequency. The performance of the proposed tracking loop is verified by several simulations.

Grid-connected converters have widely adopted LCL filters to acquire high harmonic suppression. However, the LCL filter increases the system order so that the design of the system stability would be complicated. Recently, sole-loop control strategies have been used for grid-connected converters with L or LC filters. But if the sole-loop control is directly transplanted to grid-connected converters with LCL filters, the systems may be unstable. This paper presents a novel dual-loop power control strategy composed of a power outer loop and a current inner loop. The outer loop regulates the grid-connected power. The inner loop improves the system stability margin and suppresses the resonant peak caused by the LCL filter. To obtain the control variables, a single-phase current detection is proposed based on PQ theory. The system transfer function is derived in detail and the influence of control gains on the system stability is analyzed with the root locus. Simulation and experimental results demonstrate the feasibility of the proposed control.

This paper presents an algorithm for an active power filter which can be used in both single-phase and three-phase electric system. The proposed algorithm focuses on the extraction of harmonic component of load current in each phase and in order to verify the validity of the proposed algorithm while loads are nonlinear, simulations have been done by PLECS software and tested by typhoon-HIL which is real time emulator.

In this study, we propose a real time inertial navigation system/global positioning system (INS/GPS) integrated smoothing algorithm based on an extended Kalman filter (EKF) and a position damping loop (PDL) for synthetic aperture radar (SAR). Integrated navigation algorithms usually induce discontinuities due to error correction update by the Kalman filter, which are as detrimental to the performance of SAR as the relative position error. The proposed smoothing algorithm suppresses these discontinuities and also reduces the relative position error in real time. An EKF estimates the navigation errors and sensor biases, and all the errors except for the position error are corrected directly and instantly. A PDL activated during SAR operation period imposes damping effects on the position error estimates, where the estimated position error is corrected smoothly and gradually, which contributes to the real time smoothing and small relative position errors. The residual errors are re-estimated by the EKF to maintain the estimation performance and the stability of the overall loop. The performance improvements were confirmed by Monte Carlo simulations. The simulation results showed that the discontinuities were reduced by 99.8% and the relative position error by 48% compared with a conventional EKF without a smoothing loop, thereby satisfying the basic performance requirements for SAR operation. The proposed algorithm may be applicable to low cost SAR systems which use a conventional INS/GPS without changing their hardware configurations.

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.