Earticle

Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due to the fringing field effect developed from gate to source/drain. This fringing field will further generate electric field into the channel region from source/drain region which weakens the gate control. Therefore, by taking the gate stack engineering into account it has been shown that the induced electric field along the channel can be minimized as well as the device performance can be enhanced. This paper examined various parameters of the device like potential distribution from source and drain, threshold voltage (Vth), drain induced barrier lowering (DIBL), subthreshold slope (SS), on-current (Ion), off-current (Ioff) and Transconductance (gm) by taking different dielectric materials [SiO2(ε=3.9), Si3N4 (ε=7.5), HfO2 (ε=24) and Ta2O5 (ε=50) ] as gate oxide (s).

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

이 논문에서는 field-effect mobility를 향상시키기 위해 triple-layer (SiNx/SiO2/SiOxNy stack 구조)를 gate dielectric material 로 LTPS TFTs에 적용하였다. 이는 플라즈마 처리 기법과 적층구조의 효과적인 in-situ 공정을 이용하여 interface trap과 mobile charge를 낮추어 높은 이동도의 결과를 생각하고 실험하였다. 실험은 SiO2 gatedielectric과 triple-gate dielectric의 C-V curve를 1 MHz의 주파수에서 측정하였다. 또한 Transfer characteristics를 single SiO2 gatedielectric과 triple-gate dielectric of SiNx/SiO2/SiOxNy를 STA 장비를 이용해 측정하였다. 위의 측정을 통해 threshold voltage, mobility, subtheshold swing, driving current, ON/OFF current ratio를 비교 분석하였다.

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

Scaling of the gate stack has been one of the major contributors to the performance enhancement of CMOSFET devices in past technology generations. The scalability of gate stack has diminished in recent years and alternative gate stack technology such as metal electrode and high-k dielectrics has been intensively studied during the last decade. Tody the performance of high-k dielectrics almost matches that of conventional $SiO_2-based$ gate dielectrics. However, many technical challenges remain to be resolved before alternative gate stacks can be introduced into mainstream technology. This paper reviews the research in alternative gate stack technologies to provide insights for future research.

Phase stability and morphological investigation on the $Si/SiO_2/HfO_2$ and $Si/SiO_2/ZrO_2$ stack are presented. Thermal stability of $HfO_2$ and $ZrO_2$ determines the quality of interface and subsequently the performance of device. The stacks have been fabricated and annealed at $1000^{\circ}C$ for various time. In evolution of crystalline phase and morphology (electrical and geometrical) of high-k materials, annealing time and process are observed to be crucial factors. The crystallization of some phase has been observed in the case of $Si/SiO_2/HfO_2$. The chemical environment around Zr and Hf in respective samples is observed to be different.

We investigated the effects of SiH$_4$ gas on the surface of Hf-silicate films during the deposition of polycrystalline (poly) Si films and the thermal stability of sputtered Hf-silicate films in poly Si/Hf-silicate structure by using High Resolution Transmission Electron Microscopy (HR-TEM) and X-ray Photoelectron Spectroscopy (XPS). Hf-silicate films were deposited by using DC-mag-netron sputtering with Hf target and Si target and poly Si films were deposited at 600$^{\circ}C$ by using Low Pressure Chemical Vapor Deposition (LPCVD) with SiH$_4$ gas. After poly Si film deposition at 600$^{\circ}C$, Hf silicide layer was observed between poly Si and Hf-silicate films due to the reaction between active SiH$_4$ gas and Hf-silicate films. After annealing at 900$^{\circ}C$, Hf silicide, formed during the deposition of poly Si, changed to Hf-silicate and the phase separation of the silicate was not observed. In addition, the Hf-silicate films remain amorphous phase.

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

Device makers want to make higher density chips as devices shrink, especially WSix poly stack down is one of the key issues. However, EPD (End Point Detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next generation device. To investigate the EPD time delay, a test was done with patterned wafers. This experimental was carried out combined with OES(Optical Emission Spectroscopy) and SEM (Scanning Electron Microscopy). OES was used to find corrected wavelength in WSix stack down gate etching. SEM was used to confirm WSix gate profile and gate oxide damage. Through the experiment, a new wavelength (252nm) line of plasma is selected for DPS+ chamber to call correct EPD in WSix stack down gate etching for current device and next generation device.

This paper presents an improved approach towards reducing the switching loss of insulated gate bipolar transistors (IGBTs) for a medium-capacity-class power conditioning system (PCS). In order to improve the switching performance, the switching operation is analyzed, and based on this analysis, an improved switching method that reduces the switching time and switching loss is proposed. Compared to a conventional gate drive scheme, the switching loss, switching time, and delay are improved in the proposed gate driving method. The performance of the proposed gate driving method is verified through several experiments.

최근 전자재료분야 중 고집적 소자를 다루는 분야에서는 산화규소 유전박막의 두께가 얇아짐에 따라 상부전극과 하부기판 사이에서 발생하는 누설전류가 큰 문제가 되었다. 따라서 이를 극복하기 위해 고유전상수를 가진 두꺼운 유전박막을 사용하기 시작하였는데, 그 중 대표적 인 것이 하프늄옥사이드(HfO2)와 알루미나(A12O3)이다. HfO2의 장점은 큰 유전상수를 갖는다는 것이고, A1203의 장점은 열적 안정성 이 뛰어나며, 높은 bandgap에너지를 갖는 것인데, 이 둘의 장점을 살려서 보다 편리한 방법으로 박막을 증착한 것이 바로 HfAlO이다.