Earticle

초록

영어

Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due to the fringing field effect developed from gate to source/drain. This fringing field will further generate electric field into the channel region from source/drain region which weakens the gate control. Therefore, by taking the gate stack engineering into account it has been shown that the induced electric field along the channel can be minimized as well as the device performance can be enhanced. This paper examined various parameters of the device like potential distribution from source and drain, threshold voltage (Vth), drain induced barrier lowering (DIBL), subthreshold slope (SS), on-current (Ion), off-current (Ioff) and Transconductance (gm) by taking different dielectric materials [SiO2(ε=3.9), Si3N4 (ε=7.5), HfO2 (ε=24) and Ta2O5 (ε=50) ] as gate oxide (s).

목차

Abstract
 1. Introduction
 2. Device Design and Structure
 3. Device Simulation
 4. Results and Discussion
 5. Conclusion
 References

키워드

저자

• S. K. Mohapatra [ Dept. of Electrical Engineering, National Institute of Technology, Rourkela, -769008, Odisha, India ]
• K. P. Pradhan [ Dept. of Electrical Engineering, National Institute of Technology, Rourkela, -769008, Odisha, India ]
• P. K. Sahu [ Dept. of Electrical Engineering, National Institute of Technology, Rourkela, -769008, Odisha, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605