Earticle

Our research focuses on the possibility of adversarial attacks that manipulate subtle audio signals to influence model predictions, considering the current situation where audio alterations expose security vulnerabilities. Against this backdrop, it is necessary to evaluate the impact of existing audio attacks on their detectability even under realistic physical attack conditions. In particular, our research centers on low-perceptibility attacks—such as Fade in/out, Sine mod, Bit reduction, and Hybrid attacks—that induce errors in speech recognition learning without affecting the human auditory system, aiming to identify their attack effectiveness. In the research methodology, we conducted experiments on six types of attack methods and analyzed the detection evasion capabilities and attack efficiency of the models through quantitative results, including attack success rates, prediction confidence, and visual similarity. The results revealed that recognition rates decreased in Fade in/out-based attacks, and Sine mod attacks induced emotion recognition error rates without degrading audio quality. Additionally, the Fade+ Sine modulation + Bit reduction based Hybrid attack model demonstrated the most balanced distortion and was confirmed to be the most successful in evading detection.

Flash ADC is an important component for realization of high speed and low power devices in signal processing system .As technology scale down, leakage current becomes the most concerned factor. This paper reports the power gating technique to provide the reduction mechanism for suppressing the leakage current effectively during standby mode but it introduces ground bounce noise. We designed a “3” bit flash ADC with power gating technique to reduce leakage current and ground bounce noise in different mode of operation. This diode based power gating technique provides the reduction of leakage current in standby mode, and reduction of ground bounce noise in sleep-to-active mode. The improved power gating technique provides 82% reduction in leakage current, and 73% reduction in ground bounce noise as compared with conventional flash ADC. Flash ADC with diode based stacking power gating technique has been designed with the help of cadence tool at various supply voltages with 45 nm technology.

Pilot-based coding (PBC), which is used for lossless bit rate reduction of audio coding, has been recently proposed for MPEG Surround. We propose extended PBC for further lossless bit rate reduction of MPEG Surround. Extended PBC selects the number of pilots depending on the parameter band number and the type of spatial parameter. It then encodes the pilots and the relevant difference data. Experiments show that extended PBC is more effective than the original PBC, especially for high bit rate modes, with a negligible complexity increase on the decoder side.

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

본 논문에서는 enhanced aacPlus 부호화기의 스펙트럼 계수 무손실 부호화에 arithmetic coding을 적용하여 비트율을 감소시키는 방법을 연구하였다. USAC의 arithmetic coding을 enhanced aacPlus 구조에 맞게 변경하여 적용하였다. 기존 방법과 arithmetic coding 방법에 의한 부호화 비트 수를 비교하여 성능을 평가하였고, 모노 신호에서 최대 9.3%, 스테레오 신호에서 최대 6.6%의 비트 감소율을 확인하였다.

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part so fast data transfer rate and high storage capacity about 1Tb/cm3 can be realized. In this research, to correct errors of binary data stored in holographic data storage system, a new method for reduction errors is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers. By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise in the holographic data storage system is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

In general, speech coding methods are classified into the following three categories: the waveform coding, the source coding and the hybrid coding. In this paper, First, the reference waveform is detected after searching the pitch period by NAMDF similarity and similarity between the reference waveform and the waveform each pitch period. It made a decision whether the waveform is compressed with the threshold of similarity. If the waveform is compressed only magnitude and pitch information is transmitted into the input of G.723.1 vocoder. Performing through the G.723.1 vocoder, the waveform is restored with the magnitude and pitch information by PSOLA synthesis method. The result of simulation with proposed algorithm has a 31% reduction of bit rate than the standard 5.3kbps G.723.1 ACELP vocoder.

기존의 CELP 보코더에서, 무성음에 대한 별도의 처리 없이 유성음과 동일하게 처리하였다. 유성음과 무성음은 발성모델측면에서 임펄스열과 랜덤 잡음으로 각각 다름에 도 불구하고 동일하게 처리함으로써 합성음에서 음질의 저하 및 계산량과 전송률 측면에서 손실을 가져왔다. 또, U/V(Unvoiced /voiced) 분류기를 사용하는 경우에는 U/V 분류기의 성능에 따라 합성음의 음질저하의 정도의 차이가 심하다. 본 논문에서는 에러율과 전처리 계산량을 쳐소로 할 수 있는 U/V 분류기를 사용하여 CELP 보코더에서 전송률을 감소시키는 방법을 제안한다. CELP 보코더에서는 스펙트럼 정보를 LPC 파라미터로 추출한 후 다시 전송형 파라미터인 LSP(Line Spectrum Frequency)로 변환한다 새로운 린/V 분류기는 이 LSP 파라미터를 이용한다. LSP 파라미터의 주파수영역 분포도와 간격정보를 이용하여 U/V를 결정하게 된다 제안한 방법을 5.3kbps ACELP에 적용하여 성능 평가를 실시하였다 실험결과 음질의 저하 없이 $5.6\%$ (280bps)의 전송률을 감소할 수 있었다.

저전력을 실현하기 위하여 구조, 논리 및 트랜지스터레벨에서 16비트 덧셈기를 설계하였다. 기존의 ELM덧셈기는 입력 비트 패턴에 의해 계산되는 블록캐리발생신호 (block carry generation signal) 때문에 특정 입력 비트 패턴이 인가되었을 때에는 G셀에서 글리치(glitch)가 발생하는 단점이 있다. 따라서 구조레벨에서는 특정 입력 비트 패턴에 대해서 글리치를 피하기 위해 자동적으로 각각의 블록캐리발생신호를 마지막 레벨의 G셀에 전달하는 저전력 덧셈기 구조를 제안하였다. 또한, 논리레벨에서는 정적 CMOS(static CMOS)논리형태와 저전력 XOR게이트로 구성된 저전력 소모에 적합한 조합형 논리형태(combination of logic style)를 사용하였다. 게다가 저전력을 위하여 트랜지스터레벨에서는 각 비트 전파의 논리깊이(logic depth)에 따라서 가변 크기 셀들(variable-sized cells)을 사용하였다. 0.6㎛ 단일폴리 삼중금속 LG CMOS 표준 공정변수를 가지고 16비트 덧셈기를 HSPICE로 모의 실험한 결과, 고정 크기 셀(fixed-sized cell)과 정적 CMOS 논리형태만으로 구성된 기존의 ELM 덧셈기에 비해 본 논문에서 제안된 덧셈기가 전력소모면에서는 23.6%, power-delay-product면에서는 22.6%의 향상을 보였다.

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

OFDM 기반 통신시스템에서 IFFT는 중요한 핵심 컴포넌트 중의 하나이다. 본 논문에서는 OFDM 기반 통신시스템을 위한 메모리가 효율적인 새로운 IFFT 설계 방법을 제안한다. OFDM 기반 통신시스템에서 사용되는 IFFT의 입력신호는 데이터 변조신호, 파일럿과 널(null) 신호로 구성된다. 제안한 방법은 IFFT 입력신호의 매핑을 통해 IFFT에서 가장 큰 메모리를 차지하는 비트리버스의 메모리를 감소시키는 데 초점을 둔다. 비트리버스의 메모리 크기를 감소시키기 위해 DIT기반 구조에 적합한 선택 매핑기법을 제안한다. 시뮬레이션을 통해 제안한 방법이 기존 방법과 비교하여 약 50%의 메모리가 감소됨을 보인다.

IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

본 논문에서는 채널의 전송대역폭이 제한되는 환경에서 성형 펄스로 RTPZD(root trapezoidal), RBTRC(root better than raised-cosine), 그리고 RRC(root raised-cosine)를 적용한 시스템의 BER(bit error rate) 성능을 컴퓨터 모의실험을 통하여 비교 분석하였다. 실험 결과 RBTRC는 RTPZD를 적용한 시스템보다 채널의 대역폭 제한에 더욱 민감하여, 채널의 전송대역 폭이 협소하여짐에 따라 RBTRC를 적용한 시스템의 BER 성능이 RTPZD의 성능보다 더 큰 폭으로 저하됨을 관찰할 수 있었 다. RBTRC 펄스는 심볼 타이밍 오차에 다른 성형 펄스보다 덜 민감한 장점이 있지만, 대역제한된 채널에서는 성능 저하가 크므로 성형 펄스로 RTPZD 또는 RRC 펄스를 적용하는 것이 더 유리하다고 판단된다.

본 논문은 타원곡선 암호에 핵심 연산으로 사용되는 모듈러 곱셈의 고성능 하드웨어 구현에 대해 기술한다. NIST P-521 곡선에 적합한 521-비트 고성능 모듈러 곱셈기를 3-way Toom-Cook 정수 곱셈과 고속 축약 알고리듬을 적용하여 설계하였다. 정수곱셈 결과에 3이 곱해져 출력되는 3-way Toom-Cook 알고리듬의 속성을 고려하여, 피연산자에 1/3을 곱한 Toom-Cook 도메인 상에서 모듈러 곱셈이 연산되도록 구현하였다. 모듈러 곱셈기를 xczu7ev FPGA 디바이스에 구현하여 하드웨어 동작을 검증하였으며, 69,958개의 LUT와 4,991개의 플립플롭 그리고 101개의 DSP 블록의 하드웨어 자원이 사용되었다. Zynq7 FPGA 디바이스에서 최대 동작주파수는 50 MHz으로 예측되었으며, 초당 약 416만 번의 모듈러 곱셈을 연산할 수 있는 것으로 평가되었다.

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

모듈러 곱셈은 ECC의 점 스칼라 곱셈을 위한 핵심 연산이며, ECC 프로세서의 성능에 영향을 미치는 가장 중요한 요소이다. 본 논문에서는 3-way Toom-Cook 곱셈 알고리듬과 수정된 고속 축약 알고리듬을 적용한 256-비트 모듈러 곱셈기 설계에 대해 기술한다. 90-비트 곱셈기 1개와 264-비트 가산기 3개가 사용되었으며, 하드웨어 크기와 소요 클록 사이클 수 사이의 최적화를 이루었다. Zynq UltraScale+ MPSoC 디바이스에 구현하여 모듈러 곱셈기를 검증하였으며, 모듈러 곱셈 연산에 15 클록 사이클이 소요된다.

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.