Earticle

초록

영어

Flash ADC is an important component for realization of high speed and low power devices in signal processing system .As technology scale down, leakage current becomes the most concerned factor. This paper reports the power gating technique to provide the reduction mechanism for suppressing the leakage current effectively during standby mode but it introduces ground bounce noise. We designed a “3” bit flash ADC with power gating technique to reduce leakage current and ground bounce noise in different mode of operation. This diode based power gating technique provides the reduction of leakage current in standby mode, and reduction of ground bounce noise in sleep-to-active mode. The improved power gating technique provides 82% reduction in leakage current, and 73% reduction in ground bounce noise as compared with conventional flash ADC. Flash ADC with diode based stacking power gating technique has been designed with the help of cadence tool at various supply voltages with 45 nm technology.

목차

Abstract
 1. Introduction
 2. Proposed Device Architecture
  2.1. Flash ADC
  2.2. Comparator
 3. Diode Based Stacking Power Gating Technique
  3.1. Active Mode
  3.2. Standby Mode
  3.3. Sleep to Active Mode
 4. Simulation and Performance Characteristics
  4.1. Active Power Simulation
  4.2. Leakage Current Simulation
  4.3. Leakage Power Simulation
  4.4. Ground Bounce Noise Reduction
 5. Conclusion
 Acknowledgements
 References

키워드

저자

• Swati Mishra [ Research Scholar, ITM University, Gwalior, India ]
• Shyam Akashe [ Associate Professor, ITM University, Gwalior, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Science and Technology

• 간기

  월간

• pISSN

  2005-4238

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605