Earticle

초록

영어

This paper presents an efficient summation circuit optimized for high-performance computational applications. The proposed design enables the addition of five 8-bit numbers using modular components, including add_10to4 modules and a 6-bit carry lookahead adder. The proposed circuit achieves a significant reduction in propagation delay enabling GHz-level one cycle operation. Compared to conventional ripple carry adders and carry lookahead adders, the proposed design demonstrates about 11 times speedup while maintaining a acceptable transistor overhead, contributing only 3–4% of modern processor resources. The circuit was validated through simulation in Logisim Evolution, confirming its accuracy and efficiency. Furthermore, the proposed summation circuit was successfully applied in matrix multiplication, demonstrating its potential for broader numerical computation tasks. This work provides a promising approach for integrating optimized arithmetic units into System-on-Chip (SoC) architectures, significantly enhancing computational efficiency.

목차

Abstract
1. Introduction
2. Theory
3. Experiments
4. Results and discussion
4.1 Functionality check
4.2 Comparison with Conventional Designs
5. Conclusion
Acknowledgement
References

키워드

저자

• Kibeom Kim [ Department of Electrical and Electronic Engineering, Yonam Institute of Technology, Assistant Professor, Korea ] Corresponding Author

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Advanced Culture Technology(IJACT)

• 간기

  계간

• pISSN

  2288-7202

• eISSN

  2288-7318

• 수록기간

  2013~2025

• 등재여부

  KCI 등재

• 십진분류

  KDC 600 DDC 700