In Combination logic there are some patterns which commonly occur and it is convenient to represent these in their own separate units often they are also available as separate integrated circuits. This research paper covers the two of these, the decoder and the multiplexer. In this work, designing of 2:1 MUX and MUX Based Decoder using SCL (Source Coupled Logic) is done. Power and value of current spike (Rail–to-Rail current) is found for the circuits. The Simulation is done using 180nm technology using TANNER (Version 9.2) tool.
목차
Abstract 1. Introduction 2. Decoder Circuit 3. Multiplexer Circuit 4. Source Coupled Logic (SCL) 5. Experimental Results and Proposed Methodology 5.1. Multiplexer-Minimization (MUX-MIN) Method 5.2. 2:1 MUX using SCL 5.3. Mux Based Decoder Using Scl 6. Conclusion References
키워드
MUXMUX Based DecoderSCLSCL Inverter
저자
Pooja Verma [ Department of Electronics & Communication Engineering, Tula’s Institute, Dehradun ]
Deepak Punetha [ Department of Electronics & Communication Engineering, Tula’s Institute, Dehradun ]
Yogita Bahuguna [ Department of Electronics & Communication Engineering, Tula’s Institute, Dehradun ]
보안공학연구지원센터(IJHIT) [Science & Engineering Research Support Center, Republic of Korea(IJHIT)]
설립연도
2006
분야
공학>컴퓨터학
소개
1. 보안공학에 대한 각종 조사 및 연구
2. 보안공학에 대한 응용기술 연구 및 발표
3. 보안공학에 관한 각종 학술 발표회 및 전시회 개최
4. 보안공학 기술의 상호 협조 및 정보교환
5. 보안공학에 관한 표준화 사업 및 규격의 제정
6. 보안공학에 관한 산학연 협동의 증진
7. 국제적 학술 교류 및 기술 협력
8. 보안공학에 관한 논문지 발간
9. 기타 본 회 목적 달성에 필요한 사업
간행물
간행물명
International Journal of Hybrid Information Technology
간기
격월간
pISSN
1738-9968
수록기간
2008~2016
십진분류
KDC 505DDC 605
이 권호 내 다른 논문 / International Journal of Hybrid Information Technology Vol.9 No.5